arch/powerpc/kernel/rtas_pci.c
Source file repositories/reference/linux-study-clean/arch/powerpc/kernel/rtas_pci.c
File Facts
- System
- Linux kernel
- Corpus path
arch/powerpc/kernel/rtas_pci.c- Extension
.c- Size
- 5559 bytes
- Lines
- 243
- Domain
- Architecture Layer
- Bucket
- arch/powerpc
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/kernel.hlinux/threads.hlinux/pci.hlinux/string.hlinux/init.hlinux/pgtable.hlinux/of_address.hlinux/of_fdt.hasm/io.hasm/irq.hasm/machdep.hasm/pci-bridge.hasm/iommu.hasm/rtas.hasm/mpic.hasm/ppc-pci.hasm/eeh.h
Detected Declarations
function config_access_validfunction rtas_pci_dn_read_configfunction rtas_pci_read_configfunction rtas_pci_dn_write_configfunction rtas_pci_write_configfunction is_pythonfunction python_countermeasuresfunction init_pci_config_tokensfunction get_phb_buidfunction phb_set_bus_rangesfunction rtas_setup_phb
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2001 Dave Engebretsen, IBM Corporation
* Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
*
* RTAS specific routines for PCI.
*
* Based on code from pci.c, chrp_pci.c and pSeries_pci.c
*/
#include <linux/kernel.h>
#include <linux/threads.h>
#include <linux/pci.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/pgtable.h>
#include <linux/of_address.h>
#include <linux/of_fdt.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <asm/iommu.h>
#include <asm/rtas.h>
#include <asm/mpic.h>
#include <asm/ppc-pci.h>
#include <asm/eeh.h>
/* RTAS tokens */
static int read_pci_config;
static int write_pci_config;
static int ibm_read_pci_config;
static int ibm_write_pci_config;
static inline int config_access_valid(struct pci_dn *dn, int where)
{
if (where < 256)
return 1;
if (where < 4096 && dn->pci_ext_config_space)
return 1;
return 0;
}
int rtas_pci_dn_read_config(struct pci_dn *pdn, int where, int size, u32 *val)
{
int returnval = -1;
unsigned long buid, addr;
int ret;
if (!pdn)
return PCIBIOS_DEVICE_NOT_FOUND;
if (!config_access_valid(pdn, where))
return PCIBIOS_BAD_REGISTER_NUMBER;
#ifdef CONFIG_EEH
if (pdn->edev && pdn->edev->pe &&
(pdn->edev->pe->state & EEH_PE_CFG_BLOCKED))
return PCIBIOS_SET_FAILED;
#endif
addr = rtas_config_addr(pdn->busno, pdn->devfn, where);
buid = pdn->phb->buid;
if (buid) {
ret = rtas_call(ibm_read_pci_config, 4, 2, &returnval,
addr, BUID_HI(buid), BUID_LO(buid), size);
} else {
ret = rtas_call(read_pci_config, 2, 2, &returnval, addr, size);
}
*val = returnval;
if (ret)
return PCIBIOS_DEVICE_NOT_FOUND;
return PCIBIOS_SUCCESSFUL;
}
static int rtas_pci_read_config(struct pci_bus *bus,
unsigned int devfn,
int where, int size, u32 *val)
{
struct pci_dn *pdn;
int ret;
*val = 0xFFFFFFFF;
pdn = pci_get_pdn_by_devfn(bus, devfn);
/* Validity of pdn is checked in here */
ret = rtas_pci_dn_read_config(pdn, where, size, val);
Annotation
- Immediate include surface: `linux/kernel.h`, `linux/threads.h`, `linux/pci.h`, `linux/string.h`, `linux/init.h`, `linux/pgtable.h`, `linux/of_address.h`, `linux/of_fdt.h`.
- Detected declarations: `function config_access_valid`, `function rtas_pci_dn_read_config`, `function rtas_pci_read_config`, `function rtas_pci_dn_write_config`, `function rtas_pci_write_config`, `function is_python`, `function python_countermeasures`, `function init_pci_config_tokens`, `function get_phb_buid`, `function phb_set_bus_ranges`.
- Atlas domain: Architecture Layer / arch/powerpc.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.