arch/powerpc/kernel/swsusp_85xx.S
Source file repositories/reference/linux-study-clean/arch/powerpc/kernel/swsusp_85xx.S
File Facts
- System
- Linux kernel
- Corpus path
arch/powerpc/kernel/swsusp_85xx.S- Extension
.S- Size
- 3896 bytes
- Lines
- 203
- Domain
- Architecture Layer
- Bucket
- arch/powerpc
- Inferred role
- Architecture Layer: arch/powerpc
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
linux/threads.hasm/processor.hasm/page.hasm/cputable.hasm/thread_info.hasm/ppc_asm.hasm/asm-offsets.hasm/mmu.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#include <linux/threads.h>
#include <asm/processor.h>
#include <asm/page.h>
#include <asm/cputable.h>
#include <asm/thread_info.h>
#include <asm/ppc_asm.h>
#include <asm/asm-offsets.h>
#include <asm/mmu.h>
/*
* Structure for storing CPU registers on the save area.
*/
#define SL_SP 0
#define SL_PC 4
#define SL_MSR 8
#define SL_TCR 0xc
#define SL_SPRG0 0x10
#define SL_SPRG1 0x14
#define SL_SPRG2 0x18
#define SL_SPRG3 0x1c
#define SL_SPRG4 0x20
#define SL_SPRG5 0x24
#define SL_SPRG6 0x28
#define SL_SPRG7 0x2c
#define SL_TBU 0x30
#define SL_TBL 0x34
#define SL_R2 0x38
#define SL_CR 0x3c
#define SL_LR 0x40
#define SL_R12 0x44 /* r12 to r31 */
#define SL_SIZE (SL_R12 + 80)
.section .data
.align 5
_GLOBAL(swsusp_save_area)
.space SL_SIZE
.section .text
.align 5
_GLOBAL(swsusp_arch_suspend)
lis r11,swsusp_save_area@h
ori r11,r11,swsusp_save_area@l
mflr r0
stw r0,SL_LR(r11)
mfcr r0
stw r0,SL_CR(r11)
stw r1,SL_SP(r11)
stw r2,SL_R2(r11)
stmw r12,SL_R12(r11)
/* Save MSR & TCR */
mfmsr r4
stw r4,SL_MSR(r11)
mfspr r4,SPRN_TCR
stw r4,SL_TCR(r11)
/* Get a stable timebase and save it */
1: mfspr r4,SPRN_TBRU
stw r4,SL_TBU(r11)
mfspr r5,SPRN_TBRL
stw r5,SL_TBL(r11)
mfspr r3,SPRN_TBRU
cmpw r3,r4
bne 1b
/* Save SPRGs */
Annotation
- Immediate include surface: `linux/threads.h`, `asm/processor.h`, `asm/page.h`, `asm/cputable.h`, `asm/thread_info.h`, `asm/ppc_asm.h`, `asm/asm-offsets.h`, `asm/mmu.h`.
- Atlas domain: Architecture Layer / arch/powerpc.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.