arch/powerpc/kvm/book3s_hv_rm_xics.c
Source file repositories/reference/linux-study-clean/arch/powerpc/kvm/book3s_hv_rm_xics.c
File Facts
- System
- Linux kernel
- Corpus path
arch/powerpc/kvm/book3s_hv_rm_xics.c- Extension
.c- Size
- 24074 bytes
- Lines
- 925
- Domain
- Architecture Layer
- Bucket
- arch/powerpc
- Inferred role
- Architecture Layer: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/kernel.hlinux/kvm_host.hlinux/err.hlinux/kernel_stat.hlinux/pgtable.hasm/kvm_book3s.hasm/kvm_ppc.hasm/hvcall.hasm/xics.hasm/synch.hasm/cputhreads.hasm/ppc-opcode.hasm/pnv-pci.hasm/opal.hasm/smp.hbook3s_xics.h
Detected Declarations
function ics_rm_check_resendfunction icp_send_hcore_msgfunction icp_send_hcore_msgfunction find_available_hostcorefunction icp_rm_set_vcpu_irqfunction icp_rm_clr_vcpu_irqfunction icp_rm_try_updatefunction check_too_hardfunction icp_rm_check_resendfunction icp_rm_try_to_deliverfunction icp_rm_deliver_irqfunction icp_rm_try_to_deliverfunction icp_rm_down_cpprfunction pointfunction HWfunction xics_rm_h_xirr_xfunction xics_rm_h_xirrfunction xics_rm_h_ipifunction xics_rm_h_cpprfunction attemptfunction ics_rm_eoifunction xics_rm_h_eoifunction icp_eoifunction xics_opal_set_serverfunction this_cpu_inc_rmfunction kstat_incr_irqs_this_cpufunction kvmppc_deliver_irq_passthrufunction rm_host_ipi_actionfunction kvmppc_xics_ipi_actionexport h_ipi_redirectexport kvm_irq_bypass
Annotated Snippet
static inline void icp_send_hcore_msg(int hcore, struct kvm_vcpu *vcpu) { }
#endif
/*
* We start the search from our current CPU Id in the core map
* and go in a circle until we get back to our ID looking for a
* core that is running in host context and that hasn't already
* been targeted for another rm_host_ops.
*
* In the future, could consider using a fairer algorithm (one
* that distributes the IPIs better)
*
* Returns -1, if no CPU could be found in the host
* Else, returns a CPU Id which has been reserved for use
*/
static inline int grab_next_hostcore(int start,
struct kvmppc_host_rm_core *rm_core, int max, int action)
{
bool success;
int core;
union kvmppc_rm_state old, new;
for (core = start + 1; core < max; core++) {
old = new = READ_ONCE(rm_core[core].rm_state);
if (!old.in_host || old.rm_action)
continue;
/* Try to grab this host core if not taken already. */
new.rm_action = action;
success = cmpxchg64(&rm_core[core].rm_state.raw,
old.raw, new.raw) == old.raw;
if (success) {
/*
* Make sure that the store to the rm_action is made
* visible before we return to caller (and the
* subsequent store to rm_data) to synchronize with
* the IPI handler.
*/
smp_wmb();
return core;
}
}
return -1;
}
static inline int find_available_hostcore(int action)
{
int core;
int my_core = smp_processor_id() >> threads_shift;
struct kvmppc_host_rm_core *rm_core = kvmppc_host_rm_ops_hv->rm_core;
core = grab_next_hostcore(my_core, rm_core, cpu_nr_cores(), action);
if (core == -1)
core = grab_next_hostcore(core, rm_core, my_core, action);
return core;
}
static void icp_rm_set_vcpu_irq(struct kvm_vcpu *vcpu,
struct kvm_vcpu *this_vcpu)
{
struct kvmppc_icp *this_icp = this_vcpu->arch.icp;
int cpu;
int hcore;
/* Mark the target VCPU as having an interrupt pending */
vcpu->stat.queue_intr++;
set_bit(BOOK3S_IRQPRIO_EXTERNAL, &vcpu->arch.pending_exceptions);
/* Kick self ? Just set MER and return */
if (vcpu == this_vcpu) {
mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) | LPCR_MER);
return;
}
/*
* Check if the core is loaded,
* if not, find an available host core to post to wake the VCPU,
* if we can't find one, set up state to eventually return too hard.
*/
cpu = vcpu->arch.thread_cpu;
if (cpu < 0 || cpu >= nr_cpu_ids) {
hcore = -1;
if (kvmppc_host_rm_ops_hv && h_ipi_redirect)
hcore = find_available_hostcore(XICS_RM_KICK_VCPU);
if (hcore != -1) {
icp_send_hcore_msg(hcore, vcpu);
Annotation
- Immediate include surface: `linux/kernel.h`, `linux/kvm_host.h`, `linux/err.h`, `linux/kernel_stat.h`, `linux/pgtable.h`, `asm/kvm_book3s.h`, `asm/kvm_ppc.h`, `asm/hvcall.h`.
- Detected declarations: `function ics_rm_check_resend`, `function icp_send_hcore_msg`, `function icp_send_hcore_msg`, `function find_available_hostcore`, `function icp_rm_set_vcpu_irq`, `function icp_rm_clr_vcpu_irq`, `function icp_rm_try_update`, `function check_too_hard`, `function icp_rm_check_resend`, `function icp_rm_try_to_deliver`.
- Atlas domain: Architecture Layer / arch/powerpc.
- Implementation status: integration implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.