arch/powerpc/kvm/book3s_xics.c
Source file repositories/reference/linux-study-clean/arch/powerpc/kvm/book3s_xics.c
File Facts
- System
- Linux kernel
- Corpus path
arch/powerpc/kvm/book3s_xics.c- Extension
.c- Size
- 37966 bytes
- Lines
- 1508
- Domain
- Architecture Layer
- Bucket
- arch/powerpc
- Inferred role
- Architecture Layer: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Touches user memory; correctness depends on fault-safe copying and privilege boundary handling.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/kernel.hlinux/kvm_host.hlinux/err.hlinux/gfp.hlinux/anon_inodes.hlinux/spinlock.hlinux/debugfs.hlinux/uaccess.hasm/kvm_book3s.hasm/kvm_ppc.hasm/hvcall.hasm/xics.hasm/time.hlinux/seq_file.hbook3s_xics.h
Detected Declarations
function itfunction ics_check_resendfunction write_xivefunction kvmppc_xics_set_xivefunction kvmppc_xics_get_xivefunction kvmppc_xics_int_onfunction kvmppc_xics_int_offfunction icp_try_updatefunction Acceptfunction icp_check_resendfunction icp_try_to_deliverfunction icp_deliver_irqfunction icp_try_to_deliverfunction icp_down_cpprfunction pointfunction kvmppc_h_xirrfunction kvmppc_h_ipifunction kvmppc_h_ipollfunction kvmppc_h_cpprfunction ics_eoifunction kvmppc_h_eoifunction kvmppc_xics_rm_completefunction kvmppc_xics_hcallfunction xics_debugfs_irqmapfunction xics_debug_showfunction kvm_for_each_vcpufunction xics_debugfs_initfunction kvmppc_xics_create_icpfunction kvmppc_xics_get_icpfunction kvmppc_xics_set_icpfunction xics_get_sourcefunction xics_set_sourcefunction kvmppc_xics_set_irqfunction xics_set_attrfunction xics_get_attrfunction xics_has_attrfunction kvmppc_xics_releasefunction kvmppc_xics_createfunction cpu_has_featurefunction kvmppc_xics_initfunction kvmppc_xics_connect_vcpufunction kvmppc_xics_free_icpfunction kvmppc_xics_set_mappedfunction kvmppc_xics_clr_mappedexport kvmppc_xics_rm_completeexport kvmppc_xics_hcallexport kvmppc_xics_set_mappedexport kvmppc_xics_clr_mapped
Annotated Snippet
if (state->lsi) {
if (level) {
if (pq_old & PQ_PRESENTED)
/* Setting already set LSI ... */
return 0;
pq_new = PQ_PRESENTED;
} else
pq_new = 0;
} else
pq_new = ((pq_old << 1) & 3) | PQ_PRESENTED;
} while (cmpxchg(&state->pq_state, pq_old, pq_new) != pq_old);
/* Test P=1, Q=0, this is the only case where we present */
if (pq_new == PQ_PRESENTED)
icp_deliver_irq(xics, NULL, irq, false);
/* Record which CPU this arrived on for passed-through interrupts */
if (state->host_irq)
state->intr_cpu = raw_smp_processor_id();
return 0;
}
static void ics_check_resend(struct kvmppc_xics *xics, struct kvmppc_ics *ics,
struct kvmppc_icp *icp)
{
int i;
for (i = 0; i < KVMPPC_XICS_IRQ_PER_ICS; i++) {
struct ics_irq_state *state = &ics->irq_state[i];
if (state->resend) {
XICS_DBG("resend %#x prio %#x\n", state->number,
state->priority);
icp_deliver_irq(xics, icp, state->number, true);
}
}
}
static bool write_xive(struct kvmppc_xics *xics, struct kvmppc_ics *ics,
struct ics_irq_state *state,
u32 server, u32 priority, u32 saved_priority)
{
bool deliver;
unsigned long flags;
local_irq_save(flags);
arch_spin_lock(&ics->lock);
state->server = server;
state->priority = priority;
state->saved_priority = saved_priority;
deliver = false;
if ((state->masked_pending || state->resend) && priority != MASKED) {
state->masked_pending = 0;
state->resend = 0;
deliver = true;
}
arch_spin_unlock(&ics->lock);
local_irq_restore(flags);
return deliver;
}
int kvmppc_xics_set_xive(struct kvm *kvm, u32 irq, u32 server, u32 priority)
{
struct kvmppc_xics *xics = kvm->arch.xics;
struct kvmppc_icp *icp;
struct kvmppc_ics *ics;
struct ics_irq_state *state;
u16 src;
if (!xics)
return -ENODEV;
ics = kvmppc_xics_find_ics(xics, irq, &src);
if (!ics)
return -EINVAL;
state = &ics->irq_state[src];
icp = kvmppc_xics_find_server(kvm, server);
if (!icp)
return -EINVAL;
XICS_DBG("set_xive %#x server %#x prio %#x MP:%d RS:%d\n",
irq, server, priority,
state->masked_pending, state->resend);
if (write_xive(xics, ics, state, server, priority, priority))
Annotation
- Immediate include surface: `linux/kernel.h`, `linux/kvm_host.h`, `linux/err.h`, `linux/gfp.h`, `linux/anon_inodes.h`, `linux/spinlock.h`, `linux/debugfs.h`, `linux/uaccess.h`.
- Detected declarations: `function it`, `function ics_check_resend`, `function write_xive`, `function kvmppc_xics_set_xive`, `function kvmppc_xics_get_xive`, `function kvmppc_xics_int_on`, `function kvmppc_xics_int_off`, `function icp_try_update`, `function Accept`, `function icp_check_resend`.
- Atlas domain: Architecture Layer / arch/powerpc.
- Implementation status: integration implementation candidate.
- This snippet crosses the user/kernel memory boundary; validate fault handling and access checks before translating the pattern.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.