arch/powerpc/kvm/booke.c
Source file repositories/reference/linux-study-clean/arch/powerpc/kvm/booke.c
File Facts
- System
- Linux kernel
- Corpus path
arch/powerpc/kvm/booke.c- Extension
.c- Size
- 58285 bytes
- Lines
- 2243
- Domain
- Architecture Layer
- Bucket
- arch/powerpc
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/errno.hlinux/err.hlinux/kvm_host.hlinux/gfp.hlinux/module.hlinux/vmalloc.hlinux/fs.hasm/cputable.hlinux/uaccess.hasm/interrupt.hasm/kvm_ppc.hasm/cacheflush.hasm/dbell.hasm/hw_irq.hasm/irq.hasm/time.htiming.hbooke.htrace_booke.h
Detected Declarations
function kvmppc_dump_vcpufunction kvmppc_vcpu_disable_spefunction kvmppc_vcpu_enable_spefunction kvmppc_vcpu_sync_spefunction kvmppc_vcpu_sync_spefunction kvmppc_save_guest_fpfunction kvmppc_vcpu_sync_fpufunction kvmppc_load_guest_altivecfunction kvmppc_save_guest_altivecfunction kvmppc_vcpu_sync_debugfunction kvmppc_set_msrfunction kvmppc_booke_queue_irqpriofunction kvmppc_core_queue_dtlb_missfunction kvmppc_core_queue_data_storagefunction kvmppc_core_queue_itlb_missfunction kvmppc_core_queue_inst_storagefunction kvmppc_core_queue_alignmentfunction kvmppc_core_queue_programfunction kvmppc_core_queue_fpunavailfunction kvmppc_core_queue_vec_unavailfunction kvmppc_core_queue_decfunction kvmppc_core_pending_decfunction kvmppc_core_dequeue_decfunction kvmppc_core_queue_externalfunction kvmppc_core_dequeue_externalfunction kvmppc_core_queue_watchdogfunction kvmppc_core_dequeue_watchdogfunction kvmppc_core_queue_debugfunction kvmppc_core_dequeue_debugfunction set_guest_srrfunction set_guest_csrrfunction set_guest_dsrrfunction set_guest_mcsrrfunction kvmppc_booke_irqprio_deliverfunction watchdog_next_timeoutfunction arm_next_watchdogfunction kvmppc_watchdog_funcfunction update_timer_intsfunction kvmppc_core_check_exceptionsfunction kvmppc_core_prepare_to_enterfunction kvmppc_core_check_requestsfunction kvmppc_vcpu_runfunction emulation_exitfunction kvmppc_handle_debugfunction kvmppc_fill_pt_regsfunction kvmppc_restart_interruptfunction kvmppc_resume_inst_loadfunction form
Annotated Snippet
if (!(current->thread.regs->msr & MSR_VEC)) {
enable_kernel_altivec();
load_vr_state(&vcpu->arch.vr);
disable_kernel_altivec();
current->thread.vr_save_area = &vcpu->arch.vr;
current->thread.regs->msr |= MSR_VEC;
}
}
#endif
}
/*
* Save guest vcpu AltiVec state into thread.
* It requires to be called with preemption disabled.
*/
static inline void kvmppc_save_guest_altivec(struct kvm_vcpu *vcpu)
{
#ifdef CONFIG_ALTIVEC
if (cpu_has_feature(CPU_FTR_ALTIVEC)) {
if (current->thread.regs->msr & MSR_VEC)
giveup_altivec(current);
current->thread.vr_save_area = NULL;
}
#endif
}
static void kvmppc_vcpu_sync_debug(struct kvm_vcpu *vcpu)
{
/* Synchronize guest's desire to get debug interrupts into shadow MSR */
#ifndef CONFIG_KVM_BOOKE_HV
vcpu->arch.shadow_msr &= ~MSR_DE;
vcpu->arch.shadow_msr |= vcpu->arch.shared->msr & MSR_DE;
#endif
/* Force enable debug interrupts when user space wants to debug */
if (vcpu->guest_debug) {
#ifdef CONFIG_KVM_BOOKE_HV
/*
* Since there is no shadow MSR, sync MSR_DE into the guest
* visible MSR.
*/
vcpu->arch.shared->msr |= MSR_DE;
#else
vcpu->arch.shadow_msr |= MSR_DE;
vcpu->arch.shared->msr &= ~MSR_DE;
#endif
}
}
/*
* Helper function for "full" MSR writes. No need to call this if only
* EE/CE/ME/DE/RI are changing.
*/
void kvmppc_set_msr(struct kvm_vcpu *vcpu, u32 new_msr)
{
u32 old_msr = vcpu->arch.shared->msr;
#ifdef CONFIG_KVM_BOOKE_HV
new_msr |= MSR_GS;
#endif
vcpu->arch.shared->msr = new_msr;
kvmppc_mmu_msr_notify(vcpu, old_msr);
kvmppc_vcpu_sync_spe(vcpu);
kvmppc_vcpu_sync_fpu(vcpu);
kvmppc_vcpu_sync_debug(vcpu);
}
static void kvmppc_booke_queue_irqprio(struct kvm_vcpu *vcpu,
unsigned int priority)
{
trace_kvm_booke_queue_irqprio(vcpu, priority);
set_bit(priority, &vcpu->arch.pending_exceptions);
}
void kvmppc_core_queue_dtlb_miss(struct kvm_vcpu *vcpu,
ulong dear_flags, ulong esr_flags)
{
vcpu->arch.queued_dear = dear_flags;
vcpu->arch.queued_esr = esr_flags;
kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DTLB_MISS);
}
void kvmppc_core_queue_data_storage(struct kvm_vcpu *vcpu, ulong srr1_flags,
ulong dear_flags, ulong esr_flags)
{
WARN_ON_ONCE(srr1_flags);
vcpu->arch.queued_dear = dear_flags;
vcpu->arch.queued_esr = esr_flags;
Annotation
- Immediate include surface: `linux/errno.h`, `linux/err.h`, `linux/kvm_host.h`, `linux/gfp.h`, `linux/module.h`, `linux/vmalloc.h`, `linux/fs.h`, `asm/cputable.h`.
- Detected declarations: `function kvmppc_dump_vcpu`, `function kvmppc_vcpu_disable_spe`, `function kvmppc_vcpu_enable_spe`, `function kvmppc_vcpu_sync_spe`, `function kvmppc_vcpu_sync_spe`, `function kvmppc_save_guest_fp`, `function kvmppc_vcpu_sync_fpu`, `function kvmppc_load_guest_altivec`, `function kvmppc_save_guest_altivec`, `function kvmppc_vcpu_sync_debug`.
- Atlas domain: Architecture Layer / arch/powerpc.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.