arch/powerpc/perf/e6500-pmu.c

Source file repositories/reference/linux-study-clean/arch/powerpc/perf/e6500-pmu.c

File Facts

System
Linux kernel
Corpus path
arch/powerpc/perf/e6500-pmu.c
Extension
.c
Size
3036 bytes
Lines
119
Domain
Architecture Layer
Bucket
arch/powerpc
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Performance counter support for e6500 family processors.
 *
 * Author: Priyanka Jain, Priyanka.Jain@freescale.com
 * Based on e500-pmu.c
 * Copyright 2013 Freescale Semiconductor, Inc.
 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
 */

#include <linux/string.h>
#include <linux/perf_event.h>
#include <asm/reg.h>
#include <asm/cputable.h>

/*
 * Map of generic hardware event types to hardware events
 * Zero if unsupported
 */
static int e6500_generic_events[] = {
	[PERF_COUNT_HW_CPU_CYCLES] = 1,
	[PERF_COUNT_HW_INSTRUCTIONS] = 2,
	[PERF_COUNT_HW_CACHE_MISSES] = 221,
	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 12,
	[PERF_COUNT_HW_BRANCH_MISSES] = 15,
};

#define C(x)	PERF_COUNT_HW_CACHE_##x

/*
 * Table of generalized cache-related events.
 * 0 means not supported, -1 means nonsensical, other values
 * are event codes.
 */
static int e6500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
	[C(L1D)] = {
				/*RESULT_ACCESS		RESULT_MISS */
		[C(OP_READ)] = {	27,		222	},
		[C(OP_WRITE)] = {	28,		223	},
		[C(OP_PREFETCH)] = {	29,		0	},
	},
	[C(L1I)] = {
				/*RESULT_ACCESS		RESULT_MISS */
		[C(OP_READ)] = {	2,		254	},
		[C(OP_WRITE)] = {	-1,		-1	},
		[C(OP_PREFETCH)] = {	37,		0	},
	},
	/*
	 * Assuming LL means L2, it's not a good match for this model.
	 * It does not have separate read/write events (but it does have
	 * separate instruction/data events).
	 */
	[C(LL)] = {
				/*RESULT_ACCESS		RESULT_MISS */
		[C(OP_READ)] = {	0,		0	},
		[C(OP_WRITE)] = {	0,		0	},
		[C(OP_PREFETCH)] = {	0,		0	},
	},
	/*
	 * There are data/instruction MMU misses, but that's a miss on
	 * the chip's internal level-one TLB which is probably not
	 * what the user wants.  Instead, unified level-two TLB misses
	 * are reported here.
	 */
	[C(DTLB)] = {
				/*RESULT_ACCESS		RESULT_MISS */
		[C(OP_READ)] = {	26,		66	},
		[C(OP_WRITE)] = {	-1,		-1	},
		[C(OP_PREFETCH)] = {	-1,		-1	},
	},
	[C(BPU)] = {
				/*RESULT_ACCESS		RESULT_MISS */
		[C(OP_READ)] = {	12,		15	},
		[C(OP_WRITE)] = {	-1,		-1	},
		[C(OP_PREFETCH)] = {	-1,		-1	},
	},
	[C(NODE)] = {
				/* RESULT_ACCESS	RESULT_MISS */
		[C(OP_READ)] = {	-1,		-1	},
		[C(OP_WRITE)] = {	-1,		-1	},
		[C(OP_PREFETCH)] = {	-1,		-1	},
	},
};

static int num_events = 512;

/* Upper half of event id is PMLCb, for threshold events */
static u64 e6500_xlate_event(u64 event_id)
{
	u32 event_low = (u32)event_id;

Annotation

Implementation Notes