arch/powerpc/perf/generic-compat-pmu.c

Source file repositories/reference/linux-study-clean/arch/powerpc/perf/generic-compat-pmu.c

File Facts

System
Linux kernel
Corpus path
arch/powerpc/perf/generic-compat-pmu.c
Extension
.c
Size
9427 bytes
Lines
343
Domain
Architecture Layer
Bucket
arch/powerpc
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2019 Madhavan Srinivasan, IBM Corporation.

#define pr_fmt(fmt)	"generic-compat-pmu: " fmt

#include "isa207-common.h"

/*
 * Raw event encoding:
 *
 *        60        56        52        48        44        40        36        32
 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
 *
 *        28        24        20        16        12         8         4         0
 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
 *                                 [ pmc ]                       [    pmcxsel    ]
 */

/*
 * Event codes defined in ISA v3.0B
 */
#define EVENT(_name, _code)	_name = _code,

enum {
	/* Cycles, alternate code */
	EVENT(PM_CYC_ALT,			0x100f0)
	/* One or more instructions completed in a cycle */
	EVENT(PM_CYC_INST_CMPL,			0x100f2)
	/* Floating-point instruction completed */
	EVENT(PM_FLOP_CMPL,			0x100f4)
	/* Instruction ERAT/L1-TLB miss */
	EVENT(PM_L1_ITLB_MISS,			0x100f6)
	/* All instructions completed and none available */
	EVENT(PM_NO_INST_AVAIL,			0x100f8)
	/* A load-type instruction completed (ISA v3.0+) */
	EVENT(PM_LD_CMPL,			0x100fc)
	/* Instruction completed, alternate code (ISA v3.0+) */
	EVENT(PM_INST_CMPL_ALT,			0x100fe)
	/* A store-type instruction completed */
	EVENT(PM_ST_CMPL,			0x200f0)
	/* Instruction Dispatched */
	EVENT(PM_INST_DISP,			0x200f2)
	/* Run_cycles */
	EVENT(PM_RUN_CYC,			0x200f4)
	/* Data ERAT/L1-TLB miss/reload */
	EVENT(PM_L1_DTLB_RELOAD,		0x200f6)
	/* Taken branch completed */
	EVENT(PM_BR_TAKEN_CMPL,			0x200fa)
	/* Demand iCache Miss */
	EVENT(PM_L1_ICACHE_MISS,		0x200fc)
	/* L1 Dcache reload from memory */
	EVENT(PM_L1_RELOAD_FROM_MEM,		0x200fe)
	/* L1 Dcache store miss */
	EVENT(PM_ST_MISS_L1,			0x300f0)
	/* Alternate code for PM_INST_DISP */
	EVENT(PM_INST_DISP_ALT,			0x300f2)
	/* Branch direction or target mispredicted */
	EVENT(PM_BR_MISPREDICT,			0x300f6)
	/* Data TLB miss/reload */
	EVENT(PM_DTLB_MISS,			0x300fc)
	/* Demand LD - L3 Miss (not L2 hit and not L3 hit) */
	EVENT(PM_DATA_FROM_L3MISS,		0x300fe)
	/* L1 Dcache load miss */
	EVENT(PM_LD_MISS_L1,			0x400f0)
	/* Cycle when instruction(s) dispatched */
	EVENT(PM_CYC_INST_DISP,			0x400f2)
	/* Branch or branch target mispredicted */
	EVENT(PM_BR_MPRED_CMPL,			0x400f6)
	/* Instructions completed with run latch set */
	EVENT(PM_RUN_INST_CMPL,			0x400fa)
	/* Instruction TLB miss/reload */
	EVENT(PM_ITLB_MISS,			0x400fc)
	/* Load data not cached */
	EVENT(PM_LD_NOT_CACHED,			0x400fe)
	/* Instructions */
	EVENT(PM_INST_CMPL,			0x500fa)
	/* Cycles */
	EVENT(PM_CYC,				0x600f4)
};

#undef EVENT

/* Table of alternatives, sorted in increasing order of column 0 */
/* Note that in each row, column 0 must be the smallest */
static const unsigned int generic_event_alternatives[][MAX_ALT] = {
	{ PM_CYC_ALT,			PM_CYC },
	{ PM_INST_CMPL_ALT,		PM_INST_CMPL },
	{ PM_INST_DISP,			PM_INST_DISP_ALT },
};

Annotation

Implementation Notes