arch/powerpc/platforms/44x/fsp2.h

Source file repositories/reference/linux-study-clean/arch/powerpc/platforms/44x/fsp2.h

File Facts

System
Linux kernel
Corpus path
arch/powerpc/platforms/44x/fsp2.h
Extension
.h
Size
9829 bytes
Lines
273
Domain
Architecture Layer
Bucket
arch/powerpc
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _ASM_POWERPC_FSP_DCR_H_
#define _ASM_POWERPC_FSP_DCR_H_
#ifdef __KERNEL__
#include <asm/dcr.h>

#define DCRN_CMU_ADDR		0x00C	/* Chip management unic addr */
#define DCRN_CMU_DATA		0x00D	/* Chip management unic data */

/* PLB4 Arbiter */
#define DCRN_PLB4_PCBI		0x010	/* PLB Crossbar ID/Rev Register */
#define DCRN_PLB4_P0ACR		0x011	/* PLB0 Arbiter Control Register */
#define DCRN_PLB4_P0ESRL	0x012	/* PLB0 Error Status Register Low */
#define DCRN_PLB4_P0ESRH	0x013	/* PLB0 Error Status Register High */
#define DCRN_PLB4_P0EARL	0x014	/* PLB0 Error Address Register Low */
#define DCRN_PLB4_P0EARH	0x015	/* PLB0 Error Address Register High */
#define DCRN_PLB4_P0ESRLS	0x016	/* PLB0 Error Status Register Low Set*/
#define DCRN_PLB4_P0ESRHS	0x017	/* PLB0 Error Status Register High */
#define DCRN_PLB4_PCBC		0x018	/* PLB Crossbar Control Register */
#define DCRN_PLB4_P1ACR		0x019	/* PLB1 Arbiter Control Register */
#define DCRN_PLB4_P1ESRL	0x01A	/* PLB1 Error Status Register Low */
#define DCRN_PLB4_P1ESRH	0x01B	/* PLB1 Error Status Register High */
#define DCRN_PLB4_P1EARL	0x01C	/* PLB1 Error Address Register Low */
#define DCRN_PLB4_P1EARH	0x01D	/* PLB1 Error Address Register High */
#define DCRN_PLB4_P1ESRLS	0x01E	/* PLB1 Error Status Register Low Set*/
#define DCRN_PLB4_P1ESRHS	0x01F	/*PLB1 Error Status Register High Set*/

/* PLB4/OPB bridge 0, 1, 2, 3 */
#define DCRN_PLB4OPB0_BASE	0x020
#define DCRN_PLB4OPB1_BASE	0x030
#define DCRN_PLB4OPB2_BASE	0x040
#define DCRN_PLB4OPB3_BASE	0x050

#define PLB4OPB_GESR0		0x0	/* Error status 0: Master Dev 0-3 */
#define PLB4OPB_GEAR		0x2	/* Error Address Register */
#define PLB4OPB_GEARU		0x3	/* Error Upper Address Register */
#define PLB4OPB_GESR1		0x4	/* Error Status 1: Master Dev 4-7 */
#define PLB4OPB_GESR2		0xC	/* Error Status 2: Master Dev 8-11 */

/* PLB4-to-AHB Bridge */
#define DCRN_PLB4AHB_BASE	0x400
#define DCRN_PLB4AHB_SEUAR	(DCRN_PLB4AHB_BASE + 1)
#define DCRN_PLB4AHB_SELAR	(DCRN_PLB4AHB_BASE + 2)
#define DCRN_PLB4AHB_ESR	(DCRN_PLB4AHB_BASE + 3)
#define DCRN_AHBPLB4_ESR	(DCRN_PLB4AHB_BASE + 8)
#define DCRN_AHBPLB4_EAR	(DCRN_PLB4AHB_BASE + 9)

/* PLB6 Controller */
#define DCRN_PLB6_BASE		0x11111300
#define DCRN_PLB6_CR0		(DCRN_PLB6_BASE)
#define DCRN_PLB6_ERR		(DCRN_PLB6_BASE + 0x0B)
#define DCRN_PLB6_HD		(DCRN_PLB6_BASE + 0x0E)
#define DCRN_PLB6_SHD		(DCRN_PLB6_BASE + 0x10)

/* PLB4-to-PLB6 Bridge */
#define DCRN_PLB4PLB6_BASE	0x11111320
#define DCRN_PLB4PLB6_ESR	(DCRN_PLB4PLB6_BASE + 1)
#define DCRN_PLB4PLB6_EARH	(DCRN_PLB4PLB6_BASE + 3)
#define DCRN_PLB4PLB6_EARL	(DCRN_PLB4PLB6_BASE + 4)

/* PLB6-to-PLB4 Bridge */
#define DCRN_PLB6PLB4_BASE	0x11111350
#define DCRN_PLB6PLB4_ESR	(DCRN_PLB6PLB4_BASE + 1)
#define DCRN_PLB6PLB4_EARH	(DCRN_PLB6PLB4_BASE + 3)
#define DCRN_PLB6PLB4_EARL	(DCRN_PLB6PLB4_BASE + 4)

/* PLB6-to-MCIF Bridge */
#define DCRN_PLB6MCIF_BASE	0x11111380
#define DCRN_PLB6MCIF_BESR0	(DCRN_PLB6MCIF_BASE + 0)
#define DCRN_PLB6MCIF_BESR1	(DCRN_PLB6MCIF_BASE + 1)
#define DCRN_PLB6MCIF_BEARL	(DCRN_PLB6MCIF_BASE + 2)
#define DCRN_PLB6MCIF_BEARH	(DCRN_PLB6MCIF_BASE + 3)

/* Configuration Logic Registers */
#define DCRN_CONF_BASE		0x11111400
#define DCRN_CONF_FIR_RWC	(DCRN_CONF_BASE + 0x3A)
#define DCRN_CONF_EIR_RS	(DCRN_CONF_BASE + 0x3E)
#define DCRN_CONF_RPERR0	(DCRN_CONF_BASE + 0x4D)
#define DCRN_CONF_RPERR1	(DCRN_CONF_BASE + 0x4E)

#define DCRN_L2CDCRAI		0x11111100
#define DCRN_L2CDCRDI		0x11111104
/* L2 indirect addresses */
#define L2MCK		0x120
#define L2MCKEN		0x130
#define L2INT		0x150
#define L2INTEN		0x160
#define L2LOG0		0x180
#define L2LOG1		0x184
#define L2LOG2		0x188
#define L2LOG3		0x18C

Annotation

Implementation Notes