arch/powerpc/platforms/44x/pci.c
Source file repositories/reference/linux-study-clean/arch/powerpc/platforms/44x/pci.c
File Facts
- System
- Linux kernel
- Corpus path
arch/powerpc/platforms/44x/pci.c- Extension
.c- Size
- 57939 bytes
- Lines
- 2077
- Domain
- Architecture Layer
- Bucket
- arch/powerpc
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/kernel.hlinux/pci.hlinux/init.hlinux/of.hlinux/of_address.hlinux/delay.hlinux/slab.hasm/io.hasm/pci-bridge.hasm/machdep.hasm/dcr.hasm/dcr-regs.hmm/mmu_decl.hpci.h
Detected Declarations
struct ppc4xx_pciex_portstruct ppc4xx_pciex_hwopsfunction ppc440spe_revAfunction fixup_ppc4xx_pci_bridgefunction ppc4xx_parse_dma_rangesfunction for_each_of_rangefunction ppc4xx_setup_one_pci_PMMfunction ppc4xx_configure_pci_PMMsfunction ppc4xx_configure_pci_PTMsfunction ppc4xx_probe_pci_bridgefunction ppc4xx_setup_one_pcix_POMfunction ppc4xx_configure_pcix_POMsfunction ppc4xx_configure_pcix_PIMsfunction ppc4xx_probe_pcix_bridgefunction ppc4xx_pciex_wait_on_sdrfunction ppc4xx_pciex_port_reset_sdrfunction ppc4xx_pciex_check_link_sdrfunction ppc440spe_pciex_check_resetfunction ppc440spe_pciex_core_initfunction ppc440spe_pciex_init_port_hwfunction ppc440speA_pciex_init_port_hwfunction ppc440speB_pciex_init_port_hwfunction ppc440speA_pciex_init_utlfunction ppc440speB_pciex_init_utlfunction ppc460ex_pciex_core_initfunction ppc460ex_pciex_init_port_hwfunction ppc460ex_pciex_init_utlfunction apm821xx_pciex_core_initfunction apm821xx_pciex_init_port_hwfunction ppc460sx_pciex_core_initfunction ppc460sx_pciex_init_port_hwfunction ppc460sx_pciex_init_utlfunction ppc460sx_pciex_check_linkfunction ppc_476fpe_pciex_core_initfunction ppc_476fpe_pciex_check_linkfunction ppc4xx_pciex_check_core_initfunction ppc4xx_pciex_port_init_mappingfunction ppc4xx_pciex_port_initfunction ppc4xx_pciex_wait_on_sdrfunction ppc4xx_pciex_validate_bdffunction ppc4xx_pciex_read_configfunction ppc4xx_pciex_write_configfunction ppc4xx_setup_one_pciex_POMfunction ppc4xx_configure_pciex_POMsfunction ppc4xx_configure_pciex_PIMsfunction ppc4xx_pciex_port_setup_hosefunction ppc4xx_probe_pciex_bridgefunction ppc4xx_pci_find_bridges
Annotated Snippet
of_device_is_compatible(hose->dn, "ibm,plb440grx-pci")) {
hose->indirect_type |= PPC_INDIRECT_TYPE_BROKEN_MRM;
}
/* Hide the PCI host BARs from the kernel as their content doesn't
* fit well in the resource management
*/
pci_dev_for_each_resource(dev, r) {
r->start = r->end = 0;
r->flags = 0;
}
printk(KERN_INFO "PCI: Hiding 4xx host bridge resources %s\n",
pci_name(dev));
}
DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, fixup_ppc4xx_pci_bridge);
static int __init ppc4xx_parse_dma_ranges(struct pci_controller *hose,
void __iomem *reg,
struct resource *res)
{
u64 size;
struct of_range_parser parser;
struct of_range range;
/* Default */
res->start = 0;
size = 0x80000000;
res->end = size - 1;
res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
if (of_pci_dma_range_parser_init(&parser, hose->dn))
goto out;
for_each_of_range(&parser, &range) {
u32 pci_space = range.flags;
u64 pci_addr = range.bus_addr;
u64 cpu_addr = range.cpu_addr;
size = range.size;
if (cpu_addr == OF_BAD_ADDR || size == 0)
continue;
/* We only care about memory */
if ((pci_space & 0x03000000) != 0x02000000)
continue;
/* We currently only support memory at 0, and pci_addr
* within 32 bits space
*/
if (cpu_addr != 0 || pci_addr > 0xffffffff) {
printk(KERN_WARNING "%pOF: Ignored unsupported dma range"
" 0x%016llx...0x%016llx -> 0x%016llx\n",
hose->dn,
pci_addr, pci_addr + size - 1, cpu_addr);
continue;
}
/* Check if not prefetchable */
if (!(pci_space & 0x40000000))
res->flags &= ~IORESOURCE_PREFETCH;
/* Use that */
res->start = pci_addr;
/* Beware of 32 bits resources */
if (sizeof(resource_size_t) == sizeof(u32) &&
(pci_addr + size) > 0x100000000ull)
res->end = 0xffffffff;
else
res->end = res->start + size - 1;
break;
}
/* We only support one global DMA offset */
if (dma_offset_set && pci_dram_offset != res->start) {
printk(KERN_ERR "%pOF: dma-ranges(s) mismatch\n", hose->dn);
return -ENXIO;
}
/* Check that we can fit all of memory as we don't support
* DMA bounce buffers
*/
if (size < total_memory) {
printk(KERN_ERR "%pOF: dma-ranges too small "
"(size=%llx total_memory=%llx)\n",
hose->dn, size, (u64)total_memory);
return -ENXIO;
}
Annotation
- Immediate include surface: `linux/kernel.h`, `linux/pci.h`, `linux/init.h`, `linux/of.h`, `linux/of_address.h`, `linux/delay.h`, `linux/slab.h`, `asm/io.h`.
- Detected declarations: `struct ppc4xx_pciex_port`, `struct ppc4xx_pciex_hwops`, `function ppc440spe_revA`, `function fixup_ppc4xx_pci_bridge`, `function ppc4xx_parse_dma_ranges`, `function for_each_of_range`, `function ppc4xx_setup_one_pci_PMM`, `function ppc4xx_configure_pci_PMMs`, `function ppc4xx_configure_pci_PTMs`, `function ppc4xx_probe_pci_bridge`.
- Atlas domain: Architecture Layer / arch/powerpc.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.