arch/powerpc/platforms/chrp/pegasos_eth.c
Source file repositories/reference/linux-study-clean/arch/powerpc/platforms/chrp/pegasos_eth.c
File Facts
- System
- Linux kernel
- Corpus path
arch/powerpc/platforms/chrp/pegasos_eth.c- Extension
.c- Size
- 5450 bytes
- Lines
- 205
- Domain
- Architecture Layer
- Bucket
- arch/powerpc
- Inferred role
- Architecture Layer: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/types.hlinux/init.hlinux/ioport.hlinux/device.hlinux/platform_device.hlinux/mv643xx_eth.hlinux/pci.h
Detected Declarations
function Enable_SRAMfunction mv643xx_eth_add_pdsmodule init mv643xx_eth_add_pds
Annotated Snippet
device_initcall(mv643xx_eth_add_pds);
Annotation
- Immediate include surface: `linux/types.h`, `linux/init.h`, `linux/ioport.h`, `linux/device.h`, `linux/platform_device.h`, `linux/mv643xx_eth.h`, `linux/pci.h`.
- Detected declarations: `function Enable_SRAM`, `function mv643xx_eth_add_pds`, `module init mv643xx_eth_add_pds`.
- Atlas domain: Architecture Layer / arch/powerpc.
- Implementation status: integration implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.