arch/powerpc/platforms/powernv/opal-hmi.c

Source file repositories/reference/linux-study-clean/arch/powerpc/platforms/powernv/opal-hmi.c

File Facts

System
Linux kernel
Corpus path
arch/powerpc/platforms/powernv/opal-hmi.c
Extension
.c
Size
11452 bytes
Lines
382
Domain
Architecture Layer
Bucket
arch/powerpc
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

struct OpalHmiEvtNode {
	struct list_head list;
	struct OpalHMIEvent hmi_evt;
};

struct xstop_reason {
	uint32_t xstop_reason;
	const char *unit_failed;
	const char *description;
};

static LIST_HEAD(opal_hmi_evt_list);
static DEFINE_SPINLOCK(opal_hmi_evt_lock);

static void print_core_checkstop_reason(const char *level,
					struct OpalHMIEvent *hmi_evt)
{
	int i;
	static const struct xstop_reason xstop_reason[] = {
		{ CORE_CHECKSTOP_IFU_REGFILE, "IFU",
				"RegFile core check stop" },
		{ CORE_CHECKSTOP_IFU_LOGIC, "IFU", "Logic core check stop" },
		{ CORE_CHECKSTOP_PC_DURING_RECOV, "PC",
				"Core checkstop during recovery" },
		{ CORE_CHECKSTOP_ISU_REGFILE, "ISU",
				"RegFile core check stop (mapper error)" },
		{ CORE_CHECKSTOP_ISU_LOGIC, "ISU", "Logic core check stop" },
		{ CORE_CHECKSTOP_FXU_LOGIC, "FXU", "Logic core check stop" },
		{ CORE_CHECKSTOP_VSU_LOGIC, "VSU", "Logic core check stop" },
		{ CORE_CHECKSTOP_PC_RECOV_IN_MAINT_MODE, "PC",
				"Recovery in maintenance mode" },
		{ CORE_CHECKSTOP_LSU_REGFILE, "LSU",
				"RegFile core check stop" },
		{ CORE_CHECKSTOP_PC_FWD_PROGRESS, "PC",
				"Forward Progress Error" },
		{ CORE_CHECKSTOP_LSU_LOGIC, "LSU", "Logic core check stop" },
		{ CORE_CHECKSTOP_PC_LOGIC, "PC", "Logic core check stop" },
		{ CORE_CHECKSTOP_PC_HYP_RESOURCE, "PC",
				"Hypervisor Resource error - core check stop" },
		{ CORE_CHECKSTOP_PC_HANG_RECOV_FAILED, "PC",
				"Hang Recovery Failed (core check stop)" },
		{ CORE_CHECKSTOP_PC_AMBI_HANG_DETECTED, "PC",
				"Ambiguous Hang Detected (unknown source)" },
		{ CORE_CHECKSTOP_PC_DEBUG_TRIG_ERR_INJ, "PC",
				"Debug Trigger Error inject" },
		{ CORE_CHECKSTOP_PC_SPRD_HYP_ERR_INJ, "PC",
				"Hypervisor check stop via SPRC/SPRD" },
	};

	/* Validity check */
	if (!hmi_evt->u.xstop_error.xstop_reason) {
		printk("%s	Unknown Core check stop.\n", level);
		return;
	}

	printk("%s	CPU PIR: %08x\n", level,
			be32_to_cpu(hmi_evt->u.xstop_error.u.pir));
	for (i = 0; i < ARRAY_SIZE(xstop_reason); i++)
		if (be32_to_cpu(hmi_evt->u.xstop_error.xstop_reason) &
					xstop_reason[i].xstop_reason)
			printk("%s	[Unit: %-3s] %s\n", level,
					xstop_reason[i].unit_failed,
					xstop_reason[i].description);
}

static void print_nx_checkstop_reason(const char *level,
					struct OpalHMIEvent *hmi_evt)
{
	int i;
	static const struct xstop_reason xstop_reason[] = {
		{ NX_CHECKSTOP_SHM_INVAL_STATE_ERR, "DMA & Engine",
					"SHM invalid state error" },
		{ NX_CHECKSTOP_DMA_INVAL_STATE_ERR_1, "DMA & Engine",
					"DMA invalid state error bit 15" },
		{ NX_CHECKSTOP_DMA_INVAL_STATE_ERR_2, "DMA & Engine",
					"DMA invalid state error bit 16" },
		{ NX_CHECKSTOP_DMA_CH0_INVAL_STATE_ERR, "DMA & Engine",
					"Channel 0 invalid state error" },
		{ NX_CHECKSTOP_DMA_CH1_INVAL_STATE_ERR, "DMA & Engine",
					"Channel 1 invalid state error" },
		{ NX_CHECKSTOP_DMA_CH2_INVAL_STATE_ERR, "DMA & Engine",
					"Channel 2 invalid state error" },
		{ NX_CHECKSTOP_DMA_CH3_INVAL_STATE_ERR, "DMA & Engine",
					"Channel 3 invalid state error" },
		{ NX_CHECKSTOP_DMA_CH4_INVAL_STATE_ERR, "DMA & Engine",
					"Channel 4 invalid state error" },
		{ NX_CHECKSTOP_DMA_CH5_INVAL_STATE_ERR, "DMA & Engine",
					"Channel 5 invalid state error" },
		{ NX_CHECKSTOP_DMA_CH6_INVAL_STATE_ERR, "DMA & Engine",
					"Channel 6 invalid state error" },

Annotation

Implementation Notes