arch/powerpc/platforms/powernv/vas-fault.c
Source file repositories/reference/linux-study-clean/arch/powerpc/platforms/powernv/vas-fault.c
File Facts
- System
- Linux kernel
- Corpus path
arch/powerpc/platforms/powernv/vas-fault.c- Extension
.c- Size
- 7529 bytes
- Lines
- 246
- Domain
- Architecture Layer
- Bucket
- arch/powerpc
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/kernel.hlinux/types.hlinux/slab.hlinux/uaccess.hlinux/kthread.hlinux/sched/signal.hlinux/mmu_context.hasm/icswx.hvas.h
Detected Declarations
function dump_fifofunction vas_fault_thread_fnfunction vas_fault_handlerfunction vas_setup_fault_window
Annotated Snippet
if (IS_ERR(window)) {
/*
* We got an interrupt about a specific send
* window but we can't find that window and we can't
* even clean it up (return credit on user space
* window).
* But we should not get here.
* TODO: Disable IRQ.
*/
dump_fifo(vinst, (void *)entry);
pr_err("VAS[%d] fault_fifo %p, fifo %p, pswid 0x%x, fault_crbs %d bad CRB?\n",
vinst->vas_id, vinst->fault_fifo, fifo,
be32_to_cpu(crb->stamp.nx.pswid),
vinst->fault_crbs);
WARN_ON_ONCE(1);
} else {
/*
* NX sees faults only with user space windows.
*/
if (window->user_win)
vas_update_csb(crb, &window->vas_win.task_ref);
else
WARN_ON_ONCE(!window->user_win);
/*
* Return credit for send window after processing
* fault CRB.
*/
vas_return_credit(window, true);
}
}
}
irqreturn_t vas_fault_handler(int irq, void *dev_id)
{
struct vas_instance *vinst = dev_id;
irqreturn_t ret = IRQ_WAKE_THREAD;
unsigned long flags;
/*
* NX can generate an interrupt for multiple faults. So the
* fault handler thread process all CRBs until finds invalid
* entry. In case if NX sees continuous faults, it is possible
* that the thread function entered with the first interrupt
* can execute and process all valid CRBs.
* So wake up thread only if the fault thread is not in progress.
*/
spin_lock_irqsave(&vinst->fault_lock, flags);
if (vinst->fifo_in_progress)
ret = IRQ_HANDLED;
else
vinst->fifo_in_progress = 1;
spin_unlock_irqrestore(&vinst->fault_lock, flags);
return ret;
}
/*
* Fault window is opened per VAS instance. NX pastes fault CRB in fault
* FIFO upon page faults.
*/
int vas_setup_fault_window(struct vas_instance *vinst)
{
struct vas_rx_win_attr attr;
struct vas_window *win;
vinst->fault_fifo_size = VAS_FAULT_WIN_FIFO_SIZE;
vinst->fault_fifo = kzalloc(vinst->fault_fifo_size, GFP_KERNEL);
if (!vinst->fault_fifo) {
pr_err("Unable to alloc %d bytes for fault_fifo\n",
vinst->fault_fifo_size);
return -ENOMEM;
}
/*
* Invalidate all CRB entries. NX pastes valid entry for each fault.
*/
memset(vinst->fault_fifo, FIFO_INVALID_ENTRY, vinst->fault_fifo_size);
vas_init_rx_win_attr(&attr, VAS_COP_TYPE_FAULT);
attr.rx_fifo_size = vinst->fault_fifo_size;
attr.rx_fifo = __pa(vinst->fault_fifo);
/*
* Max creds is based on number of CRBs can fit in the FIFO.
* (fault_fifo_size/CRB_SIZE). If 8MB FIFO is used, max creds
* will be 0xffff since the receive creds field is 16bits wide.
Annotation
- Immediate include surface: `linux/kernel.h`, `linux/types.h`, `linux/slab.h`, `linux/uaccess.h`, `linux/kthread.h`, `linux/sched/signal.h`, `linux/mmu_context.h`, `asm/icswx.h`.
- Detected declarations: `function dump_fifo`, `function vas_fault_thread_fn`, `function vas_fault_handler`, `function vas_setup_fault_window`.
- Atlas domain: Architecture Layer / arch/powerpc.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.