arch/powerpc/platforms/powernv/vas.h
Source file repositories/reference/linux-study-clean/arch/powerpc/platforms/powernv/vas.h
File Facts
- System
- Linux kernel
- Corpus path
arch/powerpc/platforms/powernv/vas.h- Extension
.h- Size
- 15046 bytes
- Lines
- 502
- Domain
- Architecture Layer
- Bucket
- arch/powerpc
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/atomic.hlinux/idr.hasm/vas.hlinux/io.hlinux/dcache.hlinux/mutex.hlinux/stringify.h
Detected Declarations
struct vas_instancestruct pnv_vas_windowstruct vas_winctxenum vas_notify_scopeenum vas_dma_typeenum vas_notify_after_countfunction vas_window_pidfunction vas_log_writefunction write_uwc_regfunction write_hvwc_regfunction read_hvwc_regfunction encode_pswidfunction decode_pswid
Annotated Snippet
struct vas_instance {
int vas_id;
struct ida ida;
struct list_head node;
struct platform_device *pdev;
u64 hvwc_bar_start;
u64 uwc_bar_start;
u64 paste_base_addr;
u64 paste_win_id_shift;
u64 irq_port;
int virq;
int fault_crbs;
int fault_fifo_size;
int fifo_in_progress; /* To wake up thread or return IRQ_HANDLED */
spinlock_t fault_lock; /* Protects fifo_in_progress update */
void *fault_fifo;
struct pnv_vas_window *fault_win; /* Fault window */
struct mutex mutex;
struct pnv_vas_window *rxwin[VAS_COP_TYPE_MAX];
struct pnv_vas_window *windows[VAS_WINDOWS_PER_CHIP];
char *name;
char *dbgname;
struct dentry *dbgdir;
};
/*
* In-kernel state a VAS window on PowerNV. One per window.
*/
struct pnv_vas_window {
struct vas_window vas_win;
/* Fields common to send and receive windows */
struct vas_instance *vinst;
bool tx_win; /* True if send window */
bool nx_win; /* True if NX window */
bool user_win; /* True if user space window */
void *hvwc_map; /* HV window context */
void *uwc_map; /* OS/User window context */
/* Fields applicable only to send windows */
void *paste_kaddr;
char *paste_addr_name;
struct pnv_vas_window *rxwin;
/* Fields applicable only to receive windows */
atomic_t num_txwins;
};
/*
* Container for the hardware state of a window. One per-window.
*
* A VAS Window context is a 512-byte area in the hardware that contains
* a set of 64-bit registers. Individual bit-fields in these registers
* determine the configuration/operation of the hardware. struct vas_winctx
* is a container for the register fields in the window context.
*/
struct vas_winctx {
u64 rx_fifo;
int rx_fifo_size;
int wcreds_max;
int rsvd_txbuf_count;
bool user_win;
bool nx_win;
bool fault_win;
bool rsvd_txbuf_enable;
bool pin_win;
bool rej_no_credit;
bool tx_wcred_mode;
bool rx_wcred_mode;
bool tx_word_mode;
bool rx_word_mode;
bool data_stamp;
bool xtra_write;
bool notify_disable;
bool intr_disable;
bool fifo_disable;
bool notify_early;
bool notify_os_intr_reg;
int lpid;
int pidr; /* value from SPRN_PID, not linux pid */
int lnotify_lpid;
int lnotify_pid;
int lnotify_tid;
u32 pswid;
int rx_win_id;
Annotation
- Immediate include surface: `linux/atomic.h`, `linux/idr.h`, `asm/vas.h`, `linux/io.h`, `linux/dcache.h`, `linux/mutex.h`, `linux/stringify.h`.
- Detected declarations: `struct vas_instance`, `struct pnv_vas_window`, `struct vas_winctx`, `enum vas_notify_scope`, `enum vas_dma_type`, `enum vas_notify_after_count`, `function vas_window_pid`, `function vas_log_write`, `function write_uwc_reg`, `function write_hvwc_reg`.
- Atlas domain: Architecture Layer / arch/powerpc.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.