arch/powerpc/platforms/ps3/spu.c
Source file repositories/reference/linux-study-clean/arch/powerpc/platforms/ps3/spu.c
File Facts
- System
- Linux kernel
- Corpus path
arch/powerpc/platforms/ps3/spu.c- Extension
.c- Size
- 14680 bytes
- Lines
- 621
- Domain
- Architecture Layer
- Bucket
- arch/powerpc
- Inferred role
- Architecture Layer: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/kernel.hlinux/init.hlinux/slab.hlinux/mmzone.hlinux/export.hlinux/io.hlinux/mm.hasm/spu.hasm/spu_priv1.hasm/lv1call.hasm/ps3.h../cell/spufs/spufs.hplatform.h
Detected Declarations
struct spe_shadowstruct priv1_cachestruct spu_pdatastruct tableenum spe_typeenum spe_ex_statefunction _dump_areasfunction ps3_get_spe_idfunction get_vas_idfunction construct_spufunction spu_unmapfunction setup_areasfunction setup_interruptsfunction enable_spufunction ps3_destroy_spufunction ps3_create_spufunction ps3_enumerate_spusfunction ps3_init_affinityfunction ps3_enable_spufunction int_mask_andfunction int_mask_orfunction int_mask_setfunction int_mask_getfunction int_stat_clearfunction int_stat_getfunction cpu_affinity_setfunction mfc_dsisr_setfunction mfc_sdr_setupfunction mfc_sr1_getfunction mfc_tclass_id_setfunction mfc_tclass_id_getfunction tlb_invalidatefunction resource_allocation_enable_setfunction ps3_spu_set_platformexport ps3_get_spe_id
Annotated Snippet
struct spe_shadow {
u8 padding_0140[0x0140];
u64 int_status_class0_RW; /* 0x0140 */
u64 int_status_class1_RW; /* 0x0148 */
u64 int_status_class2_RW; /* 0x0150 */
u8 padding_0158[0x0610-0x0158];
u64 mfc_dsisr_RW; /* 0x0610 */
u8 padding_0618[0x0620-0x0618];
u64 mfc_dar_RW; /* 0x0620 */
u8 padding_0628[0x0800-0x0628];
u64 mfc_dsipr_R; /* 0x0800 */
u8 padding_0808[0x0810-0x0808];
u64 mfc_lscrr_R; /* 0x0810 */
u8 padding_0818[0x0c00-0x0818];
u64 mfc_cer_R; /* 0x0c00 */
u8 padding_0c08[0x0f00-0x0c08];
u64 spe_execution_status; /* 0x0f00 */
u8 padding_0f08[0x1000-0x0f08];
};
/**
* enum spe_ex_state - Logical spe execution state.
* @SPE_EX_STATE_UNEXECUTABLE: Uninitialized.
* @SPE_EX_STATE_EXECUTABLE: Enabled, not ready.
* @SPE_EX_STATE_EXECUTED: Ready for use.
*
* The execution state (status) of the logical spe as reported in
* struct spe_shadow:spe_execution_status.
*/
enum spe_ex_state {
SPE_EX_STATE_UNEXECUTABLE = 0,
SPE_EX_STATE_EXECUTABLE = 2,
SPE_EX_STATE_EXECUTED = 3,
};
/**
* struct priv1_cache - Cached values of priv1 registers.
* @masks[]: Array of cached spe interrupt masks, indexed by class.
* @sr1: Cached mfc_sr1 register.
* @tclass_id: Cached mfc_tclass_id register.
*/
struct priv1_cache {
u64 masks[3];
u64 sr1;
u64 tclass_id;
};
/**
* struct spu_pdata - Platform state variables.
* @spe_id: HV spe id returned by lv1_construct_logical_spe().
* @resource_id: HV spe resource id returned by
* ps3_repository_read_spe_resource_id().
* @priv2_addr: lpar address of spe priv2 area returned by
* lv1_construct_logical_spe().
* @shadow_addr: lpar address of spe register shadow area returned by
* lv1_construct_logical_spe().
* @shadow: Virtual (ioremap) address of spe register shadow area.
* @cache: Cached values of priv1 registers.
*/
struct spu_pdata {
u64 spe_id;
u64 resource_id;
u64 priv2_addr;
u64 shadow_addr;
struct spe_shadow __iomem *shadow;
struct priv1_cache cache;
};
static struct spu_pdata *spu_pdata(struct spu *spu)
{
return spu->pdata;
}
#define dump_areas(_a, _b, _c, _d, _e) \
_dump_areas(_a, _b, _c, _d, _e, __func__, __LINE__)
static void _dump_areas(unsigned int spe_id, unsigned long priv2,
unsigned long problem, unsigned long ls, unsigned long shadow,
const char* func, int line)
{
pr_debug("%s:%d: spe_id: %xh (%u)\n", func, line, spe_id, spe_id);
pr_debug("%s:%d: priv2: %lxh\n", func, line, priv2);
pr_debug("%s:%d: problem: %lxh\n", func, line, problem);
pr_debug("%s:%d: ls: %lxh\n", func, line, ls);
pr_debug("%s:%d: shadow: %lxh\n", func, line, shadow);
}
u64 ps3_get_spe_id(void *arg)
Annotation
- Immediate include surface: `linux/kernel.h`, `linux/init.h`, `linux/slab.h`, `linux/mmzone.h`, `linux/export.h`, `linux/io.h`, `linux/mm.h`, `asm/spu.h`.
- Detected declarations: `struct spe_shadow`, `struct priv1_cache`, `struct spu_pdata`, `struct table`, `enum spe_type`, `enum spe_ex_state`, `function _dump_areas`, `function ps3_get_spe_id`, `function get_vas_id`, `function construct_spu`.
- Atlas domain: Architecture Layer / arch/powerpc.
- Implementation status: integration implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.