arch/powerpc/sysdev/fsl_rio.h
Source file repositories/reference/linux-study-clean/arch/powerpc/sysdev/fsl_rio.h
File Facts
- System
- Linux kernel
- Corpus path
arch/powerpc/sysdev/fsl_rio.h- Extension
.h- Size
- 4119 bytes
- Lines
- 146
- Domain
- Architecture Layer
- Bucket
- arch/powerpc
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/rio.hlinux/rio_drv.hlinux/kfifo.h
Detected Declarations
struct rio_atmu_regsstruct rio_inb_atmu_regsstruct rio_dbell_ringstruct rio_port_write_msgstruct fsl_rio_dbellstruct fsl_rio_pwstruct rio_priv
Annotated Snippet
struct rio_atmu_regs {
u32 rowtar;
u32 rowtear;
u32 rowbar;
u32 pad1;
u32 rowar;
u32 pad2[3];
};
struct rio_inb_atmu_regs {
u32 riwtar;
u32 pad1;
u32 riwbar;
u32 pad2;
u32 riwar;
u32 pad3[3];
};
struct rio_dbell_ring {
void *virt;
dma_addr_t phys;
};
struct rio_port_write_msg {
void *virt;
dma_addr_t phys;
u32 msg_count;
u32 err_count;
u32 discard_count;
};
struct fsl_rio_dbell {
struct rio_mport *mport[MAX_PORT_NUM];
struct device *dev;
struct rio_dbell_regs __iomem *dbell_regs;
struct rio_dbell_ring dbell_ring;
int bellirq;
};
struct fsl_rio_pw {
struct rio_mport *mport[MAX_PORT_NUM];
struct device *dev;
struct rio_pw_regs __iomem *pw_regs;
struct rio_port_write_msg port_write_msg;
int pwirq;
struct work_struct pw_work;
struct kfifo pw_fifo;
spinlock_t pw_fifo_lock;
};
struct rio_priv {
struct device *dev;
void __iomem *regs_win;
struct rio_atmu_regs __iomem *atmu_regs;
struct rio_atmu_regs __iomem *maint_atmu_regs;
struct rio_inb_atmu_regs __iomem *inb_atmu_regs;
void __iomem *maint_win;
void *rmm_handle; /* RapidIO message manager(unit) Handle */
};
extern void __iomem *rio_regs_win;
extern void __iomem *rmu_regs_win;
extern resource_size_t rio_law_start;
extern struct fsl_rio_dbell *dbell;
extern struct fsl_rio_pw *pw;
extern int fsl_rio_setup_rmu(struct rio_mport *mport,
struct device_node *node);
extern int fsl_rio_port_write_init(struct fsl_rio_pw *pw);
extern int fsl_rio_pw_enable(struct rio_mport *mport, int enable);
extern void fsl_rio_port_error_handler(int offset);
extern int fsl_rio_doorbell_init(struct fsl_rio_dbell *dbell);
extern int fsl_rio_doorbell_send(struct rio_mport *mport,
int index, u16 destid, u16 data);
extern int fsl_add_outb_message(struct rio_mport *mport,
struct rio_dev *rdev,
int mbox, void *buffer, size_t len);
extern int fsl_open_outb_mbox(struct rio_mport *mport,
void *dev_id, int mbox, int entries);
extern void fsl_close_outb_mbox(struct rio_mport *mport, int mbox);
extern int fsl_open_inb_mbox(struct rio_mport *mport,
void *dev_id, int mbox, int entries);
extern void fsl_close_inb_mbox(struct rio_mport *mport, int mbox);
extern int fsl_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf);
extern void *fsl_get_inb_message(struct rio_mport *mport, int mbox);
#endif
Annotation
- Immediate include surface: `linux/rio.h`, `linux/rio_drv.h`, `linux/kfifo.h`.
- Detected declarations: `struct rio_atmu_regs`, `struct rio_inb_atmu_regs`, `struct rio_dbell_ring`, `struct rio_port_write_msg`, `struct fsl_rio_dbell`, `struct fsl_rio_pw`, `struct rio_priv`.
- Atlas domain: Architecture Layer / arch/powerpc.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.