arch/powerpc/sysdev/mpic.c
Source file repositories/reference/linux-study-clean/arch/powerpc/sysdev/mpic.c
File Facts
- System
- Linux kernel
- Corpus path
arch/powerpc/sysdev/mpic.c- Extension
.c- Size
- 52309 bytes
- Lines
- 2023
- Domain
- Architecture Layer
- Bucket
- arch/powerpc
- Inferred role
- Architecture Layer: operation-table or driver-model contract
- Status
- pattern implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Defines an operation table; this is where Linux turns generic core objects into subsystem-specific behavior.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/types.hlinux/kernel.hlinux/init.hlinux/irq.hlinux/smp.hlinux/interrupt.hlinux/spinlock.hlinux/pci.hlinux/slab.hlinux/string_choices.hlinux/syscore_ops.hlinux/ratelimit.hlinux/pgtable.hlinux/of_address.hlinux/of_irq.hasm/ptrace.hasm/signal.hasm/io.hasm/irq.hasm/machdep.hasm/mpic.hasm/smp.hmpic.h
Detected Declarations
function mpic_processor_idfunction _mpic_readfunction _mpic_writefunction _mpic_ipi_readfunction _mpic_ipi_writefunction mpic_tm_offsetfunction _mpic_tm_readfunction _mpic_tm_writefunction _mpic_cpu_readfunction _mpic_cpu_writefunction _mpic_irq_readfunction _mpic_irq_writefunction _mpic_map_mmiofunction _mpic_map_dcrfunction mpic_mapfunction mpic_test_broken_ipifunction mpic_is_ht_interruptfunction mpic_ht_end_irqfunction mpic_startup_ht_interruptfunction mpic_shutdown_ht_interruptfunction mpic_scan_ht_msifunction mpic_scan_ht_msifunction mpic_scan_ht_picfunction mpic_scan_ht_picsfunction mpic_is_ht_interruptfunction mpic_scan_ht_picsfunction mpic_is_ipifunction mpic_is_tmfunction mpic_physmaskfunction mpic_from_ipifunction mpic_from_irqfunction mpic_from_irq_datafunction mpic_eoifunction mpic_unmask_irqfunction mpic_mask_irqfunction mpic_end_irqfunction mpic_unmask_ht_irqfunction mpic_startup_ht_irqfunction mpic_shutdown_ht_irqfunction mpic_end_ht_irqfunction mpic_unmask_ipifunction mpic_mask_ipifunction mpic_unmask_tmfunction mpic_mask_tmfunction mpic_set_affinityfunction mpic_type_to_vecprifunction mpic_set_irq_typefunction mpic_set_vector
Annotated Snippet
const struct bus_type mpic_subsys = {
.name = "mpic",
.dev_name = "mpic",
};
EXPORT_SYMBOL_GPL(mpic_subsys);
static struct mpic *mpics;
static struct mpic *mpic_primary;
static DEFINE_RAW_SPINLOCK(mpic_lock);
#ifdef CONFIG_PPC32 /* XXX for now */
#ifdef CONFIG_IRQ_ALL_CPUS
#define distribute_irqs (1)
#else
#define distribute_irqs (0)
#endif
#endif
#ifdef CONFIG_MPIC_WEIRD
static u32 mpic_infos[][MPIC_IDX_END] = {
[0] = { /* Original OpenPIC compatible MPIC */
MPIC_GREG_BASE,
MPIC_GREG_FEATURE_0,
MPIC_GREG_GLOBAL_CONF_0,
MPIC_GREG_VENDOR_ID,
MPIC_GREG_IPI_VECTOR_PRI_0,
MPIC_GREG_IPI_STRIDE,
MPIC_GREG_SPURIOUS,
MPIC_GREG_TIMER_FREQ,
MPIC_TIMER_BASE,
MPIC_TIMER_STRIDE,
MPIC_TIMER_CURRENT_CNT,
MPIC_TIMER_BASE_CNT,
MPIC_TIMER_VECTOR_PRI,
MPIC_TIMER_DESTINATION,
MPIC_CPU_BASE,
MPIC_CPU_STRIDE,
MPIC_CPU_IPI_DISPATCH_0,
MPIC_CPU_IPI_DISPATCH_STRIDE,
MPIC_CPU_CURRENT_TASK_PRI,
MPIC_CPU_WHOAMI,
MPIC_CPU_INTACK,
MPIC_CPU_EOI,
MPIC_CPU_MCACK,
MPIC_IRQ_BASE,
MPIC_IRQ_STRIDE,
MPIC_IRQ_VECTOR_PRI,
MPIC_VECPRI_VECTOR_MASK,
MPIC_VECPRI_POLARITY_POSITIVE,
MPIC_VECPRI_POLARITY_NEGATIVE,
MPIC_VECPRI_SENSE_LEVEL,
MPIC_VECPRI_SENSE_EDGE,
MPIC_VECPRI_POLARITY_MASK,
MPIC_VECPRI_SENSE_MASK,
MPIC_IRQ_DESTINATION
},
[1] = { /* Tsi108/109 PIC */
TSI108_GREG_BASE,
TSI108_GREG_FEATURE_0,
TSI108_GREG_GLOBAL_CONF_0,
TSI108_GREG_VENDOR_ID,
TSI108_GREG_IPI_VECTOR_PRI_0,
TSI108_GREG_IPI_STRIDE,
TSI108_GREG_SPURIOUS,
TSI108_GREG_TIMER_FREQ,
TSI108_TIMER_BASE,
TSI108_TIMER_STRIDE,
TSI108_TIMER_CURRENT_CNT,
TSI108_TIMER_BASE_CNT,
TSI108_TIMER_VECTOR_PRI,
TSI108_TIMER_DESTINATION,
TSI108_CPU_BASE,
TSI108_CPU_STRIDE,
TSI108_CPU_IPI_DISPATCH_0,
TSI108_CPU_IPI_DISPATCH_STRIDE,
TSI108_CPU_CURRENT_TASK_PRI,
TSI108_CPU_WHOAMI,
TSI108_CPU_INTACK,
TSI108_CPU_EOI,
TSI108_CPU_MCACK,
TSI108_IRQ_BASE,
TSI108_IRQ_STRIDE,
TSI108_IRQ_VECTOR_PRI,
TSI108_VECPRI_VECTOR_MASK,
Annotation
- Immediate include surface: `linux/types.h`, `linux/kernel.h`, `linux/init.h`, `linux/irq.h`, `linux/smp.h`, `linux/interrupt.h`, `linux/spinlock.h`, `linux/pci.h`.
- Detected declarations: `function mpic_processor_id`, `function _mpic_read`, `function _mpic_write`, `function _mpic_ipi_read`, `function _mpic_ipi_write`, `function mpic_tm_offset`, `function _mpic_tm_read`, `function _mpic_tm_write`, `function _mpic_cpu_read`, `function _mpic_cpu_write`.
- Atlas domain: Architecture Layer / arch/powerpc.
- Implementation status: pattern implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.