arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
Source file repositories/reference/linux-study-clean/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts- Extension
.dts- Size
- 5302 bytes
- Lines
- 252
- Domain
- Architecture Layer
- Bucket
- arch/riscv
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/gpio/gpio.hdt-bindings/input/input.hdt-bindings/leds/common.hsun20i-d1.dtsisun20i-common-regulators.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
/*
* gpio line names
*
* The Nezha-D1 has a 40-pin IO header. Some of these pins are routed
* directly to pads on the SoC, others come from an 8-bit pcf857x IO
* expander. Therefore, these line names are specified in two places:
* one set for the pcf857x, and one set for the pio controller.
*
* Lines which are routed to the 40-pin header are named as follows:
* <pin#> [<pin name>]
* where:
* <pin#> is the actual pin number of the 40-pin header
* <pin name> is the name of the pin by function/gpio#
*
* For details regarding pin numbers and names see the schematics (under
* "IO EXPAND"):
* http://dl.linux-sunxi.org/D1/D1_Nezha_development_board_schematic_diagram_20210224.pdf
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/dts-v1/;
#include "sun20i-d1.dtsi"
#include "sun20i-common-regulators.dtsi"
/ {
model = "Allwinner D1 Nezha";
compatible = "allwinner,d1-nezha", "allwinner,sun20i-d1";
aliases {
ethernet0 = &emac;
ethernet1 = &xr829;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
reg_usbvbus: usbvbus {
compatible = "regulator-fixed";
regulator-name = "usbvbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
enable-active-high;
vin-supply = <®_vcc>;
};
/*
* This regulator is PWM-controlled, but the PWM controller is not
* yet supported, so fix the regulator to its default voltage.
*/
reg_vdd_cpu: vdd-cpu {
compatible = "regulator-fixed";
regulator-name = "vdd-cpu";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
vin-supply = <®_vcc>;
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
Annotation
- Immediate include surface: `dt-bindings/gpio/gpio.h`, `dt-bindings/input/input.h`, `dt-bindings/leds/common.h`, `sun20i-d1.dtsi`, `sun20i-common-regulators.dtsi`.
- Atlas domain: Architecture Layer / arch/riscv.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.