arch/riscv/boot/dts/andes/qilai.dtsi

Source file repositories/reference/linux-study-clean/arch/riscv/boot/dts/andes/qilai.dtsi

File Facts

System
Linux kernel
Corpus path
arch/riscv/boot/dts/andes/qilai.dtsi
Extension
.dtsi
Size
4818 bytes
Lines
187
Domain
Architecture Layer
Bucket
arch/riscv
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2025 Andes Technology Corporation. All rights reserved.
 */

/dts-v1/;

#include <dt-bindings/interrupt-controller/irq.h>

/ {
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		timebase-frequency = <62500000>;

		cpu0: cpu@0 {
			compatible = "andestech,ax45mp", "riscv";
			device_type = "cpu";
			reg = <0>;
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "zicntr", "zicsr", "zifencei",
					       "zihpm", "xandespmu";
			mmu-type = "riscv,sv39";
			clock-frequency = <100000000>;
			i-cache-size = <0x8000>;
			i-cache-sets = <256>;
			i-cache-line-size = <64>;
			d-cache-size = <0x8000>;
			d-cache-sets = <128>;
			d-cache-line-size = <64>;
			next-level-cache = <&l2_cache>;

			cpu0_intc: interrupt-controller {
				compatible = "andestech,cpu-intc", "riscv,cpu-intc";
				#interrupt-cells = <1>;
				interrupt-controller;
			};
		};

		cpu1: cpu@1 {
			compatible = "andestech,ax45mp", "riscv";
			device_type = "cpu";
			reg = <1>;
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "zicntr", "zicsr", "zifencei",
					       "zihpm", "xandespmu";
			mmu-type = "riscv,sv39";
			clock-frequency = <100000000>;
			i-cache-size = <0x8000>;
			i-cache-sets = <256>;
			i-cache-line-size = <64>;
			d-cache-size = <0x8000>;
			d-cache-sets = <128>;
			d-cache-line-size = <64>;
			next-level-cache = <&l2_cache>;

			cpu1_intc: interrupt-controller {
				compatible = "andestech,cpu-intc",
					     "riscv,cpu-intc";
				#interrupt-cells = <1>;
				interrupt-controller;
			};
		};

		cpu2: cpu@2 {

Annotation

Implementation Notes