arch/riscv/boot/dts/anlogic/dr1v90.dtsi

Source file repositories/reference/linux-study-clean/arch/riscv/boot/dts/anlogic/dr1v90.dtsi

File Facts

System
Linux kernel
Corpus path
arch/riscv/boot/dts/anlogic/dr1v90.dtsi
Extension
.dtsi
Size
2584 bytes
Lines
102
Domain
Architecture Layer
Bucket
arch/riscv
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
 * Copyright (C) 2025 Junhui Liu <junhui.liu@pigmoral.tech>
 */

/dts-v1/;
/ {
	#address-cells = <2>;
	#size-cells = <2>;
	model = "Anlogic DR1V90";
	compatible = "anlogic,dr1v90";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		timebase-frequency = <800000000>;

		cpu@0 {
			compatible = "nuclei,ux900", "riscv";
			d-cache-block-size = <64>;
			d-cache-sets = <256>;
			d-cache-size = <32768>;
			device_type = "cpu";
			i-cache-block-size = <64>;
			i-cache-sets = <256>;
			i-cache-size = <32768>;
			mmu-type = "riscv,sv39";
			reg = <0>;
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b",
					       "zba", "zbb", "zbc", "zbkc", "zbs",
					       "zicntr", "zicsr", "zifencei",
					       "zihintpause", "zihpm";

			cpu0_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				#interrupt-cells = <1>;
				interrupt-controller;
			};
		};
	};

	soc {
		compatible = "simple-bus";
		interrupt-parent = <&plic>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		aclint_mswi: interrupt-controller@68031000 {
			compatible = "anlogic,dr1v90-aclint-mswi", "nuclei,ux900-aclint-mswi";
			reg = <0x0 0x68031000 0x0 0x4000>;
			interrupts-extended = <&cpu0_intc 3>;
		};

		aclint_mtimer: timer@68035000 {
			compatible = "anlogic,dr1v90-aclint-mtimer", "nuclei,ux900-aclint-mtimer";
			reg = <0x0 0x68035000 0x0 0x8000>;
			reg-names = "mtimecmp";
			interrupts-extended = <&cpu0_intc 7>;
		};

		aclint_sswi: interrupt-controller@6803d000 {
			compatible = "anlogic,dr1v90-aclint-sswi", "nuclei,ux900-aclint-sswi";
			reg = <0x0 0x6803d000 0x0 0x3000>;
			#interrupt-cells = <0>;
			interrupt-controller;
			interrupts-extended = <&cpu0_intc 1>;
		};

Annotation

Implementation Notes