arch/riscv/boot/dts/canaan/k210.dtsi

Source file repositories/reference/linux-study-clean/arch/riscv/boot/dts/canaan/k210.dtsi

File Facts

System
Linux kernel
Corpus path
arch/riscv/boot/dts/canaan/k210.dtsi
Extension
.dtsi
Size
13022 bytes
Lines
511
Domain
Architecture Layer
Bucket
arch/riscv
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
 * Copyright (C) 2020 Western Digital Corporation or its affiliates.
 */
#include <dt-bindings/clock/k210-clk.h>
#include <dt-bindings/pinctrl/k210-fpioa.h>
#include <dt-bindings/reset/k210-rst.h>

/ {
	/*
	 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
	 * wide, and the upper half of all addresses is ignored.
	 */
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "canaan,kendryte-k210";

	/*
	 * The K210 has an sv39 MMU following the privileged specification v1.9.
	 * Since this is a non-ratified draft specification, the kernel does not
	 * support it and the K210 support enabled only for the !MMU case.
	 * Be consistent with this by setting the CPUs MMU type to "none".
	 */
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		timebase-frequency = <7800000>;
		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "canaan,k210", "riscv";
			reg = <0>;
			riscv,isa = "rv64imafdc";
			mmu-type = "riscv,none";
			i-cache-block-size = <64>;
			i-cache-size = <0x8000>;
			d-cache-block-size = <64>;
			d-cache-size = <0x8000>;
			cpu0_intc: interrupt-controller {
				#interrupt-cells = <1>;
				interrupt-controller;
				compatible = "riscv,cpu-intc";
			};
		};
		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "canaan,k210", "riscv";
			reg = <1>;
			riscv,isa = "rv64imafdc";
			mmu-type = "riscv,none";
			i-cache-block-size = <64>;
			i-cache-size = <0x8000>;
			d-cache-block-size = <64>;
			d-cache-size = <0x8000>;
			cpu1_intc: interrupt-controller {
				#interrupt-cells = <1>;
				interrupt-controller;
				compatible = "riscv,cpu-intc";
			};
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};

				core1 {
					cpu = <&cpu1>;
				};

Annotation

Implementation Notes