arch/riscv/boot/dts/eswin/eic7700.dtsi

Source file repositories/reference/linux-study-clean/arch/riscv/boot/dts/eswin/eic7700.dtsi

File Facts

System
Linux kernel
Corpus path
arch/riscv/boot/dts/eswin/eic7700.dtsi
Extension
.dtsi
Size
8896 bytes
Lines
346
Domain
Architecture Layer
Bucket
arch/riscv
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (c) 2024 Beijing ESWIN Computing Technology Co., Ltd.
 */

/dts-v1/;

/ {
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		timebase-frequency = <1000000>;

		cpu0: cpu@0 {
			compatible = "sifive,p550", "riscv";
			device_type = "cpu";
			d-cache-block-size = <64>;
			d-cache-sets = <128>;
			d-cache-size = <32768>;
			d-tlb-sets = <1>;
			d-tlb-size = <32>;
			i-cache-block-size = <64>;
			i-cache-sets = <128>;
			i-cache-size = <32768>;
			i-tlb-sets = <1>;
			i-tlb-size = <32>;
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache_0>;
			reg = <0x0>;
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "sscofpmf",
					       "zba", "zbb", "zicsr", "zifencei";
			tlb-split;

			cpu0_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				#interrupt-cells = <1>;
				interrupt-controller;
			};
		};

		cpu1: cpu@1 {
			compatible = "sifive,p550", "riscv";
			d-cache-block-size = <64>;
			d-cache-sets = <128>;
			d-cache-size = <32768>;
			d-tlb-sets = <1>;
			d-tlb-size = <32>;
			device_type = "cpu";
			i-cache-block-size = <64>;
			i-cache-sets = <128>;
			i-cache-size = <32768>;
			i-tlb-sets = <1>;
			i-tlb-size = <32>;
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache_1>;
			reg = <0x1>;
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "sscofpmf",
					       "zba", "zbb", "zicsr", "zifencei";
			tlb-split;

			cpu1_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				#interrupt-cells = <1>;
				interrupt-controller;
			};

Annotation

Implementation Notes