arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi

Source file repositories/reference/linux-study-clean/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi

File Facts

System
Linux kernel
Corpus path
arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
Extension
.dtsi
Size
3313 bytes
Lines
143
Domain
Architecture Layer
Bucket
arch/riscv
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2020-2021 Microchip Technology Inc */

#include "mpfs.dtsi"
#include "mpfs-pinctrl.dtsi"

/ {
	core_pwm0: pwm@40000000 {
		compatible = "microchip,corepwm-rtl-v4";
		reg = <0x0 0x40000000 0x0 0xF0>;
		microchip,sync-update-mask = /bits/ 32 <0>;
		#pwm-cells = <3>;
		clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>;
		status = "disabled";
	};

	i2c2: i2c@40000200 {
		compatible = "microchip,corei2c-rtl-v7";
		reg = <0x0 0x40000200 0x0 0x100>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>;
		interrupt-parent = <&plic>;
		interrupts = <122>;
		clock-frequency = <100000>;
		status = "disabled";
	};

	ihc: mailbox {
		compatible = "microchip,sbi-ipc";
		interrupt-parent = <&plic>;
		interrupts = <180>, <179>, <178>, <177>;
		interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4";
		#mbox-cells = <1>;
		status = "disabled";
	};

	mailbox@50000000 {
		compatible = "microchip,miv-ihc-rtl-v2";
		reg = <0x0 0x50000000 0x0 0x1c000>;
		interrupt-parent = <&plic>;
		interrupts = <180>, <179>, <178>, <177>;
		interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4";
		#mbox-cells = <1>;
		microchip,ihc-chan-disabled-mask = /bits/ 16 <0>;
		status = "disabled";
	};

	pcie: pcie@3000000000 {
		compatible = "microchip,pcie-host-1.0";
		#address-cells = <0x3>;
		#interrupt-cells = <0x1>;
		#size-cells = <0x2>;
		device_type = "pci";
		reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43008000 0x0 0x2000>,
		      <0x0 0x4300a000 0x0 0x2000>;
		reg-names = "cfg", "bridge", "ctrl";
		bus-range = <0x0 0x7f>;
		interrupt-parent = <&plic>;
		interrupts = <119>;
		interrupt-map = <0 0 0 1 &pcie_intc 0>,
				<0 0 0 2 &pcie_intc 1>,
				<0 0 0 3 &pcie_intc 2>,
				<0 0 0 4 &pcie_intc 3>;
		interrupt-map-mask = <0 0 0 7>;
		clocks = <&ccc_nw CLK_CCC_PLL0_OUT1>, <&ccc_nw CLK_CCC_PLL0_OUT3>;
		clock-names = "fic1", "fic3";
		ranges = <0x3000000 0x0 0x8000000 0x30 0x8000000 0x0 0x80000000>;
		dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>;
		msi-parent = <&pcie>;

Annotation

Implementation Notes