arch/riscv/boot/dts/microchip/pic64gx.dtsi

Source file repositories/reference/linux-study-clean/arch/riscv/boot/dts/microchip/pic64gx.dtsi

File Facts

System
Linux kernel
Corpus path
arch/riscv/boot/dts/microchip/pic64gx.dtsi
Extension
.dtsi
Size
17543 bytes
Lines
657
Domain
Architecture Layer
Bucket
arch/riscv
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Source for the PIC64GX SoCs
 *
 * Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
 *
 * Author: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
 *
 * PIC64GX is a series RISC-V multicore SoCs:
 * https://www.microchip.com/en-us/products/microprocessors/64-bit-mpus/pic64gx
 */

/dts-v1/;
#include "dt-bindings/clock/microchip,mpfs-clock.h"

/ {
	#address-cells = <2>;
	#size-cells = <2>;
	model = "Microchip PIC64GX SoC";
	compatible = "microchip,pic64gx";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "sifive,e51", "sifive,rocket0", "riscv";
			device_type = "cpu";
			i-cache-block-size = <64>;
			i-cache-sets = <128>;
			i-cache-size = <16384>;
			reg = <0>;
			riscv,isa = "rv64imac";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr",
					       "zifencei", "zihpm";
			clocks = <&clkcfg CLK_CPU>;
			status = "disabled";

			cpu0_intc: interrupt-controller {
				#interrupt-cells = <1>;
				compatible = "riscv,cpu-intc";
				interrupt-controller;
			};
		};

		cpu1: cpu@1 {
			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
			d-cache-block-size = <64>;
			d-cache-sets = <64>;
			d-cache-size = <32768>;
			d-tlb-sets = <1>;
			d-tlb-size = <32>;
			device_type = "cpu";
			i-cache-block-size = <64>;
			i-cache-sets = <64>;
			i-cache-size = <32768>;
			i-tlb-sets = <1>;
			i-tlb-size = <32>;
			mmu-type = "riscv,sv39";
			reg = <1>;
			riscv,isa = "rv64imafdc";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr",
					       "zicsr", "zifencei", "zihpm";
			clocks = <&clkcfg CLK_CPU>;
			tlb-split;
			next-level-cache = <&cctrllr>;
			status = "okay";

Annotation

Implementation Notes