arch/riscv/boot/dts/sifive/fu740-c000.dtsi

Source file repositories/reference/linux-study-clean/arch/riscv/boot/dts/sifive/fu740-c000.dtsi

File Facts

System
Linux kernel
Corpus path
arch/riscv/boot/dts/sifive/fu740-c000.dtsi
Extension
.dtsi
Size
9965 bytes
Lines
366
Domain
Architecture Layer
Bucket
arch/riscv
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2020 SiFive, Inc */

/dts-v1/;

#include <dt-bindings/clock/sifive-fu740-prci.h>

/ {
	#address-cells = <2>;
	#size-cells = <2>;
	compatible = "sifive,fu740-c000", "sifive,fu740";

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		ethernet0 = &eth0;
	};

	chosen {
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu0: cpu@0 {
			compatible = "sifive,bullet0", "riscv";
			device_type = "cpu";
			i-cache-block-size = <64>;
			i-cache-sets = <128>;
			i-cache-size = <16384>;
			next-level-cache = <&ccache>;
			reg = <0x0>;
			riscv,isa = "rv64imac";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
					       "zihpm";
			status = "disabled";
			cpu0_intc: interrupt-controller {
				#interrupt-cells = <1>;
				compatible = "riscv,cpu-intc";
				interrupt-controller;
			};
		};
		cpu1: cpu@1 {
			compatible = "sifive,bullet0", "riscv";
			d-cache-block-size = <64>;
			d-cache-sets = <64>;
			d-cache-size = <32768>;
			d-tlb-sets = <1>;
			d-tlb-size = <40>;
			device_type = "cpu";
			i-cache-block-size = <64>;
			i-cache-sets = <128>;
			i-cache-size = <32768>;
			i-tlb-sets = <1>;
			i-tlb-size = <40>;
			mmu-type = "riscv,sv39";
			next-level-cache = <&ccache>;
			reg = <0x1>;
			riscv,isa = "rv64imafdc";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
					       "zifencei", "zihpm";
			tlb-split;
			cpu1_intc: interrupt-controller {
				#interrupt-cells = <1>;
				compatible = "riscv,cpu-intc";
				interrupt-controller;
			};
		};

Annotation

Implementation Notes