arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi

Source file repositories/reference/linux-study-clean/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi

File Facts

System
Linux kernel
Corpus path
arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi
Extension
.dtsi
Size
91472 bytes
Lines
3158
Domain
Architecture Layer
Bucket
arch/riscv
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2025 Inochi Amaoto <inochiama@gmail.com>
 */

/ {
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		timebase-frequency = <50000000>;

		cpu0: cpu@0 {
			compatible = "thead,c920", "riscv";
			reg = <0x0>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache0>;
			riscv,isa = "rv64imafdcbv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "b", "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",
					       "zicbom", "zicbop", "zicboz", "ziccrse",
					       "zicntr", "zicond","zicsr", "zifencei",
					       "zihintntl", "zihintpause", "zihpm",
					       "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;

			cpu0_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu1: cpu@1 {
			compatible = "thead,c920", "riscv";
			reg = <0x1>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			device_type = "cpu";
			mmu-type = "riscv,sv48";
			next-level-cache = <&l2_cache0>;
			riscv,isa = "rv64imafdcbv";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "b", "v", "sscofpmf", "sstc",
					       "svinval", "svnapot", "svpbmt",
					       "zawrs", "zba", "zbb", "zbc",
					       "zbs", "zca", "zcb", "zcd",
					       "zfa", "zfbfmin", "zfh", "zfhmin",

Annotation

Implementation Notes