arch/riscv/boot/dts/sophgo/sg2044.dtsi

Source file repositories/reference/linux-study-clean/arch/riscv/boot/dts/sophgo/sg2044.dtsi

File Facts

System
Linux kernel
Corpus path
arch/riscv/boot/dts/sophgo/sg2044.dtsi
Extension
.dtsi
Size
17104 bytes
Lines
586
Domain
Architecture Layer
Bucket
arch/riscv
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2025 Inochi Amaoto <inochiama@gmail.com>
 */

#include <dt-bindings/clock/sophgo,sg2044-pll.h>
#include <dt-bindings/clock/sophgo,sg2044-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-sg2044.h>

#include "sg2044-cpus.dtsi"
#include "sg2044-reset.h"

/ {
	compatible = "sophgo,sg2044";

	memory@80000000 {
		device_type = "memory";
		reg = <0x00000000 0x80000000 0x00000010 0x00000000>;
	};

	osc: oscillator {
		compatible = "fixed-clock";
		clock-output-names = "osc";
		#clock-cells = <0>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		pcie0: pcie@6c00000000 {
			compatible = "sophgo,sg2044-pcie";
			reg = <0x6c 0x00000000 0x0 0x00001000>,
			      <0x6c 0x00300000 0x0 0x00004000>,
			      <0x48 0x00000000 0x0 0x00001000>,
			      <0x6c 0x000c0000 0x0 0x00001000>;
			reg-names = "dbi", "atu", "config", "app";
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;
			clocks = <&clk CLK_GATE_PCIE_1G>;
			clock-names = "core";
			device_type = "pci";
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
					<0 0 0 2 &pcie_intc0 1>,
					<0 0 0 3 &pcie_intc0 2>,
					<0 0 0 4 &pcie_intc0 3>;
			msi-parent = <&msi>;
			ranges = <0x01000000 0x0  0x00000000  0x48 0x10000000  0x0 0x00200000>,
				 <0x42000000 0x0  0x10000000  0x0  0x10000000  0x0 0x04000000>,
				 <0x02000000 0x0  0x14000000  0x0  0x14000000  0x0 0x04000000>,
				 <0x43000000 0x4a 0x00000000  0x4a 0x00000000  0x2 0x00000000>,
				 <0x03000000 0x49 0x00000000  0x49 0x00000000  0x1 0x00000000>;
			status = "disabled";

			pcie_intc0: interrupt-controller {
				#address-cells = <0>;
				#interrupt-cells = <1>;
				interrupt-parent = <&intc>;
				interrupts = <65 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-controller;
			};
		};

		pcie1: pcie@6c00400000 {

Annotation

Implementation Notes