arch/riscv/boot/dts/spacemit/k3.dtsi

Source file repositories/reference/linux-study-clean/arch/riscv/boot/dts/spacemit/k3.dtsi

File Facts

System
Linux kernel
Corpus path
arch/riscv/boot/dts/spacemit/k3.dtsi
Extension
.dtsi
Size
37104 bytes
Lines
1191
Domain
Architecture Layer
Bucket
arch/riscv
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd
 * Copyright (c) 2026 Guodong Xu <guodong@riscstar.com>
 */

#include <dt-bindings/clock/spacemit,k3-clocks.h>
#include <dt-bindings/reset/spacemit,k3-resets.h>
#include <dt-bindings/interrupt-controller/irq.h>

/dts-v1/;

/ {
	#address-cells = <2>;
	#size-cells = <2>;
	model = "SpacemiT K3";
	compatible = "spacemit,k3";

	cpus: cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		timebase-frequency = <24000000>;

		cpu_0: cpu@0 {
			compatible = "spacemit,x100", "riscv";
			device_type = "cpu";
			reg = <0>;
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
					       "sha", "shcounterenw", "shgatpa", "shtvala",
					       "shvsatpa", "shvstvala", "shvstvecd", "smaia",
					       "smstateen", "ssaia", "ssccptr", "sscofpmf",
					       "sscounterenw", "ssnpm", "ssstateen", "sstc",
					       "sstvala", "sstvecd", "ssu64xl", "svade",
					       "svinval", "svnapot", "svpbmt", "za64rs",
					       "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
					       "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
					       "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
					       "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr",
					       "zicond", "zicsr", "zifencei", "zihintntl",
					       "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
					       "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
					       "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
					       "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
					       "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
			riscv,cbom-block-size = <64>;
			riscv,cbop-block-size = <64>;
			riscv,cboz-block-size = <64>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <256>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <256>;
			next-level-cache = <&l2_cache0>;
			mmu-type = "riscv,sv39";

			cpu0_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				#interrupt-cells = <1>;
				interrupt-controller;
			};
		};

		cpu_1: cpu@1 {
			compatible = "spacemit,x100", "riscv";
			device_type = "cpu";
			reg = <1>;
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",

Annotation

Implementation Notes