arch/riscv/boot/dts/starfive/jh7110.dtsi

Source file repositories/reference/linux-study-clean/arch/riscv/boot/dts/starfive/jh7110.dtsi

File Facts

System
Linux kernel
Corpus path
arch/riscv/boot/dts/starfive/jh7110.dtsi
Extension
.dtsi
Size
37556 bytes
Lines
1307
Domain
Architecture Layer
Bucket
arch/riscv
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
 * Copyright (C) 2022 StarFive Technology Co., Ltd.
 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
 */

/dts-v1/;
#include <dt-bindings/clock/starfive,jh7110-crg.h>
#include <dt-bindings/power/starfive,jh7110-pmu.h>
#include <dt-bindings/reset/starfive,jh7110-crg.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	compatible = "starfive,jh7110";
	#address-cells = <2>;
	#size-cells = <2>;

	cpus: cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		S7_0: cpu@0 {
			compatible = "sifive,s7", "riscv";
			reg = <0>;
			device_type = "cpu";
			i-cache-block-size = <64>;
			i-cache-sets = <64>;
			i-cache-size = <16384>;
			next-level-cache = <&ccache>;
			riscv,isa = "rv64imac_zba_zbb";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "c", "zba", "zbb", "zicntr", "zicsr",
					       "zifencei", "zihpm";
			status = "disabled";

			cpu0_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				bootph-pre-ram;
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		U74_1: cpu@1 {
			compatible = "sifive,u74-mc", "riscv";
			reg = <1>;
			d-cache-block-size = <64>;
			d-cache-sets = <64>;
			d-cache-size = <32768>;
			d-tlb-sets = <1>;
			d-tlb-size = <40>;
			device_type = "cpu";
			i-cache-block-size = <64>;
			i-cache-sets = <64>;
			i-cache-size = <32768>;
			i-tlb-sets = <1>;
			i-tlb-size = <40>;
			mmu-type = "riscv,sv39";
			next-level-cache = <&ccache>;
			riscv,isa = "rv64imafdc_zba_zbb";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
					       "zicsr", "zifencei", "zihpm";
			tlb-split;
			operating-points-v2 = <&cpu_opp>;
			clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
			clock-names = "cpu";
			#cooling-cells = <2>;

			cpu1_intc: interrupt-controller {

Annotation

Implementation Notes