arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dtsi
Source file repositories/reference/linux-study-clean/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dtsi- Extension
.dtsi- Size
- 2988 bytes
- Lines
- 162
- Domain
- Architecture Layer
- Bucket
- arch/riscv
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
jh7110-common.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2025 StarFive Technology Co., Ltd.
* Copyright (C) 2025 Hal Feng <hal.feng@starfivetech.com>
*/
/dts-v1/;
#include "jh7110-common.dtsi"
/ {
vcc_3v3_pcie: regulator-vcc-3v3-pcie {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&sysgpio 27 GPIO_ACTIVE_HIGH>;
regulator-name = "vcc_3v3_pcie";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&cpu_opp {
/delete-node/ opp-375000000;
/delete-node/ opp-500000000;
/delete-node/ opp-750000000;
/delete-node/ opp-1500000000;
opp-312500000 {
opp-hz = /bits/ 64 <312500000>;
opp-microvolt = <800000>;
};
opp-417000000 {
opp-hz = /bits/ 64 <417000000>;
opp-microvolt = <800000>;
};
opp-625000000 {
opp-hz = /bits/ 64 <625000000>;
opp-microvolt = <800000>;
};
opp-1250000000 {
opp-hz = /bits/ 64 <1250000000>;
opp-microvolt = <1000000>;
};
};
&gmac0 {
starfive,tx-use-rgmii-clk;
assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
status = "okay";
};
&i2c0 {
status = "okay";
};
&mmc1 {
max-frequency = <50000000>;
keep-power-in-suspend;
non-removable;
};
&pcie1 {
vpcie3v3-supply = <&vcc_3v3_pcie>;
status = "okay";
};
&phy0 {
motorcomm,tx-clk-adj-enabled;
motorcomm,tx-clk-100-inverted;
motorcomm,tx-clk-1000-inverted;
Annotation
- Immediate include surface: `jh7110-common.dtsi`.
- Atlas domain: Architecture Layer / arch/riscv.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.