arch/riscv/boot/dts/tenstorrent/blackhole.dtsi

Source file repositories/reference/linux-study-clean/arch/riscv/boot/dts/tenstorrent/blackhole.dtsi

File Facts

System
Linux kernel
Corpus path
arch/riscv/boot/dts/tenstorrent/blackhole.dtsi
Extension
.dtsi
Size
4627 bytes
Lines
157
Domain
Architecture Layer
Bucket
arch/riscv
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
// Copyright 2025 Tenstorrent AI ULC
/dts-v1/;

/ {
	compatible = "tenstorrent,blackhole";
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		timebase-frequency = <50000000>;

		cpu@0 {
			compatible = "sifive,x280", "sifive,rocket0", "riscv";
			device_type = "cpu";
			reg = <0>;
			mmu-type = "riscv,sv57";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
					       "zifencei", "zfh", "zba", "zbb", "sscofpmf";

			cpu0_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				#interrupt-cells = <1>;
				interrupt-controller;
			};
		};

		cpu@1 {
			compatible = "sifive,x280", "sifive,rocket0", "riscv";
			device_type = "cpu";
			reg = <1>;
			mmu-type = "riscv,sv57";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
					       "zifencei", "zfh", "zba", "zbb", "sscofpmf";

			cpu1_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				#interrupt-cells = <1>;
				interrupt-controller;
			};
		};

		cpu@2 {
			compatible = "sifive,x280", "sifive,rocket0", "riscv";
			device_type = "cpu";
			reg = <2>;
			mmu-type = "riscv,sv57";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
					       "zifencei", "zfh", "zba", "zbb", "sscofpmf";

			cpu2_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				#interrupt-cells = <1>;
				interrupt-controller;
			};
		};

		cpu@3 {
			compatible = "sifive,x280", "sifive,rocket0", "riscv";
			device_type = "cpu";
			reg = <3>;
			mmu-type = "riscv,sv57";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
					       "zifencei", "zfh", "zba", "zbb", "sscofpmf";

Annotation

Implementation Notes