arch/riscv/include/asm/ftrace.h
Source file repositories/reference/linux-study-clean/arch/riscv/include/asm/ftrace.h
File Facts
- System
- Linux kernel
- Corpus path
arch/riscv/include/asm/ftrace.h- Extension
.h- Size
- 6523 bytes
- Lines
- 243
- Domain
- Architecture Layer
- Bucket
- arch/riscv
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
struct dyn_arch_ftracestruct dyn_ftracestruct ftrace_opsstruct ftrace_regsstruct __arch_ftrace_regsfunction arch_trace_is_compat_syscallfunction arch_syscall_match_sym_namefunction ftrace_regs_get_instruction_pointerfunction ftrace_regs_set_instruction_pointerfunction ftrace_regs_get_stack_pointerfunction ftrace_regs_get_frame_pointerfunction ftrace_regs_get_argumentfunction ftrace_regs_get_return_valuefunction ftrace_regs_get_return_addressfunction ftrace_regs_set_return_valuefunction ftrace_override_function_with_returnfunction ftrace_partial_regsfunction arch_ftrace_set_direct_caller
Annotated Snippet
struct dyn_arch_ftrace {
};
#endif
#ifdef CONFIG_DYNAMIC_FTRACE
/*
* A general call in RISC-V is a pair of insts:
* 1) auipc: setting high-20 pc-related bits to ra register
* 2) jalr: setting low-12 offset to ra, jump to ra, and set ra to
* return address (original pc + 4)
*
* The first 2 instructions for each tracable function is compiled to 2 nop
* instructions. Then, the kernel initializes the first instruction to auipc at
* boot time (<ftrace disable>). The second instruction is patched to jalr to
* start the trace.
*
*<Image>:
* 0: nop
* 4: nop
*
*<ftrace enable>:
* 0: auipc t0, 0x?
* 4: jalr t0, ?(t0)
*
*<ftrace disable>:
* 0: auipc t0, 0x?
* 4: nop
*
* Dynamic ftrace generates probes to call sites, so we must deal with
* both auipc and jalr at the same time.
*/
#define MCOUNT_ADDR ((unsigned long)_mcount)
#define JALR_SIGN_MASK (0x00000800)
#define JALR_OFFSET_MASK (0x00000fff)
#define AUIPC_OFFSET_MASK (0xfffff000)
#define AUIPC_PAD (0x00001000)
#define JALR_SHIFT 20
#define JALR_T0 (0x000282e7)
#define AUIPC_T0 (0x00000297)
#define JALR_RANGE (JALR_SIGN_MASK - 1)
#define to_jalr_t0(offset) \
(((offset & JALR_OFFSET_MASK) << JALR_SHIFT) | JALR_T0)
#define to_auipc_t0(offset) \
((offset & JALR_SIGN_MASK) ? \
(((offset & AUIPC_OFFSET_MASK) + AUIPC_PAD) | AUIPC_T0) : \
((offset & AUIPC_OFFSET_MASK) | AUIPC_T0))
#define make_call_t0(caller, callee, call) \
do { \
unsigned int offset = \
(unsigned long) (callee) - (unsigned long) (caller); \
call[0] = to_auipc_t0(offset); \
call[1] = to_jalr_t0(offset); \
} while (0)
/*
* Only the jalr insn in the auipc+jalr is patched, so we make it 4
* bytes here.
*/
#define MCOUNT_INSN_SIZE 4
#define MCOUNT_AUIPC_SIZE 4
#define MCOUNT_JALR_SIZE 4
#define MCOUNT_NOP4_SIZE 4
#ifndef __ASSEMBLER__
struct dyn_ftrace;
int ftrace_init_nop(struct module *mod, struct dyn_ftrace *rec);
#define ftrace_init_nop ftrace_init_nop
#ifdef CONFIG_DYNAMIC_FTRACE_WITH_ARGS
#define arch_ftrace_get_regs(regs) NULL
#define HAVE_ARCH_FTRACE_REGS
struct ftrace_ops;
struct ftrace_regs;
#define arch_ftrace_regs(fregs) ((struct __arch_ftrace_regs *)(fregs))
struct __arch_ftrace_regs {
unsigned long epc;
unsigned long ra;
unsigned long sp;
unsigned long s0;
unsigned long t1;
#ifdef CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS
unsigned long direct_tramp;
#endif
union {
unsigned long args[8];
Annotation
- Detected declarations: `struct dyn_arch_ftrace`, `struct dyn_ftrace`, `struct ftrace_ops`, `struct ftrace_regs`, `struct __arch_ftrace_regs`, `function arch_trace_is_compat_syscall`, `function arch_syscall_match_sym_name`, `function ftrace_regs_get_instruction_pointer`, `function ftrace_regs_set_instruction_pointer`, `function ftrace_regs_get_stack_pointer`.
- Atlas domain: Architecture Layer / arch/riscv.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.