arch/riscv/include/asm/insn-def.h

Source file repositories/reference/linux-study-clean/arch/riscv/include/asm/insn-def.h

File Facts

System
Linux kernel
Corpus path
arch/riscv/include/asm/insn-def.h
Extension
.h
Size
10515 bytes
Lines
352
Domain
Architecture Layer
Bucket
arch/riscv
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __ASM_INSN_DEF_H
#define __ASM_INSN_DEF_H

#include <asm/asm.h>

#define INSN_R_FUNC7_SHIFT		25
#define INSN_R_RS2_SHIFT		20
#define INSN_R_RS1_SHIFT		15
#define INSN_R_FUNC3_SHIFT		12
#define INSN_R_RD_SHIFT			 7
#define INSN_R_OPCODE_SHIFT		 0

#define INSN_I_SIMM12_SHIFT		20
#define INSN_I_RS1_SHIFT		15
#define INSN_I_FUNC3_SHIFT		12
#define INSN_I_RD_SHIFT			 7
#define INSN_I_OPCODE_SHIFT		 0

#define INSN_S_SIMM7_SHIFT		25
#define INSN_S_RS2_SHIFT		20
#define INSN_S_RS1_SHIFT		15
#define INSN_S_FUNC3_SHIFT		12
#define INSN_S_SIMM5_SHIFT		 7
#define INSN_S_OPCODE_SHIFT		 0

#ifdef __ASSEMBLER__

#ifdef CONFIG_AS_HAS_INSN

	.macro insn_r, opcode, func3, func7, rd, rs1, rs2
	.insn	r \opcode, \func3, \func7, \rd, \rs1, \rs2
	.endm

	.macro insn_i, opcode, func3, rd, rs1, simm12
	.insn	i \opcode, \func3, \rd, \rs1, \simm12
	.endm

	.macro insn_s, opcode, func3, rs2, simm12, rs1
	.insn	s \opcode, \func3, \rs2, \simm12(\rs1)
	.endm

#else

#include <asm/gpr-num.h>

	.macro insn_r, opcode, func3, func7, rd, rs1, rs2
	.4byte	((\opcode << INSN_R_OPCODE_SHIFT) |		\
		 (\func3 << INSN_R_FUNC3_SHIFT) |		\
		 (\func7 << INSN_R_FUNC7_SHIFT) |		\
		 (.L__gpr_num_\rd << INSN_R_RD_SHIFT) |		\
		 (.L__gpr_num_\rs1 << INSN_R_RS1_SHIFT) |	\
		 (.L__gpr_num_\rs2 << INSN_R_RS2_SHIFT))
	.endm

	.macro insn_i, opcode, func3, rd, rs1, simm12
	.4byte	((\opcode << INSN_I_OPCODE_SHIFT) |		\
		 (\func3 << INSN_I_FUNC3_SHIFT) |		\
		 (.L__gpr_num_\rd << INSN_I_RD_SHIFT) |		\
		 (.L__gpr_num_\rs1 << INSN_I_RS1_SHIFT) |	\
		 (\simm12 << INSN_I_SIMM12_SHIFT))
	.endm

	.macro insn_s, opcode, func3, rs2, simm12, rs1
	.4byte	((\opcode << INSN_S_OPCODE_SHIFT) |		\
		 (\func3 << INSN_S_FUNC3_SHIFT) |		\
		 (.L__gpr_num_\rs2 << INSN_S_RS2_SHIFT) |	\
		 (.L__gpr_num_\rs1 << INSN_S_RS1_SHIFT) |	\
		 ((\simm12 & 0x1f) << INSN_S_SIMM5_SHIFT) |	\
		 (((\simm12 >> 5) & 0x7f) << INSN_S_SIMM7_SHIFT))
	.endm

#endif

#define __INSN_R(...)	insn_r __VA_ARGS__
#define __INSN_I(...)	insn_i __VA_ARGS__
#define __INSN_S(...)	insn_s __VA_ARGS__

#else /* ! __ASSEMBLER__ */

#ifdef CONFIG_AS_HAS_INSN

#define __INSN_R(opcode, func3, func7, rd, rs1, rs2)	\
	".insn	r " opcode ", " func3 ", " func7 ", " rd ", " rs1 ", " rs2 "\n"

#define __INSN_I(opcode, func3, rd, rs1, simm12)	\
	".insn	i " opcode ", " func3 ", " rd ", " rs1 ", " simm12 "\n"

#define __INSN_S(opcode, func3, rs2, simm12, rs1)	\
	".insn	s " opcode ", " func3 ", " rs2 ", " simm12 "(" rs1 ")\n"

Annotation

Implementation Notes