arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h
Source file repositories/reference/linux-study-clean/arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h
File Facts
- System
- Linux kernel
- Corpus path
arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h- Extension
.h- Size
- 663 bytes
- Lines
- 35
- Domain
- Architecture Layer
- Bucket
- arch/riscv
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
asm/sbi.h
Detected Declarations
struct kvm_sbi_fwft_featurestruct kvm_sbi_fwft_configstruct kvm_sbi_fwft
Annotated Snippet
struct kvm_sbi_fwft_config {
const struct kvm_sbi_fwft_feature *feature;
bool supported;
bool enabled;
unsigned long flags;
};
/* FWFT data structure per vcpu */
struct kvm_sbi_fwft {
struct kvm_sbi_fwft_config *configs;
#ifndef CONFIG_32BIT
bool have_vs_pmlen_7;
bool have_vs_pmlen_16;
#endif
};
#define vcpu_to_fwft(vcpu) (&(vcpu)->arch.fwft_context)
#endif /* !__KVM_VCPU_RISCV_FWFT_H */
Annotation
- Immediate include surface: `asm/sbi.h`.
- Detected declarations: `struct kvm_sbi_fwft_feature`, `struct kvm_sbi_fwft_config`, `struct kvm_sbi_fwft`.
- Atlas domain: Architecture Layer / arch/riscv.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.