arch/riscv/include/uapi/asm/sigcontext.h
Source file repositories/reference/linux-study-clean/arch/riscv/include/uapi/asm/sigcontext.h
File Facts
- System
- Linux kernel
- Corpus path
arch/riscv/include/uapi/asm/sigcontext.h- Extension
.h- Size
- 948 bytes
- Lines
- 42
- Domain
- Architecture Layer
- Bucket
- arch/riscv
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
asm/ptrace.h
Detected Declarations
struct __sc_riscv_v_statestruct sigcontext
Annotated Snippet
struct __sc_riscv_v_state {
struct __riscv_v_ext_state v_state;
} __attribute__((aligned(16)));
/*
* Signal context structure
*
* This contains the context saved before a signal handler is invoked;
* it is restored by sys_rt_sigreturn.
*/
struct sigcontext {
struct user_regs_struct sc_regs;
union {
union __riscv_fp_state sc_fpregs;
struct __riscv_extra_ext_header sc_extdesc;
};
};
#endif /*!__ASSEMBLER__*/
#endif /* _UAPI_ASM_RISCV_SIGCONTEXT_H */
Annotation
- Immediate include surface: `asm/ptrace.h`.
- Detected declarations: `struct __sc_riscv_v_state`, `struct sigcontext`.
- Atlas domain: Architecture Layer / arch/riscv.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.