arch/riscv/Kconfig.errata

Source file repositories/reference/linux-study-clean/arch/riscv/Kconfig.errata

File Facts

System
Linux kernel
Corpus path
arch/riscv/Kconfig.errata
Extension
.errata
Size
4962 bytes
Lines
158
Domain
Architecture Layer
Bucket
arch/riscv
Inferred role
Architecture Layer: arch/riscv
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

menu "CPU errata selection"

config ERRATA_ANDES
	bool "Andes AX45MP errata"
	depends on RISCV_ALTERNATIVE && RISCV_SBI
	help
	  All Andes errata Kconfig depend on this Kconfig. Disabling
	  this Kconfig will disable all Andes errata. Please say "Y"
	  here if your platform uses Andes CPU cores.

	  Otherwise, please say "N" here to avoid unnecessary overhead.

config ERRATA_ANDES_CMO
	bool "Apply Andes cache management errata"
	depends on ERRATA_ANDES && ARCH_R9A07G043
	select RISCV_DMA_NONCOHERENT
	default y
	help
	  This will apply the cache management errata to handle the
	  non-standard handling on non-coherent operations on Andes cores.

	  If you don't know what to do here, say "Y".

config ERRATA_MIPS
	bool "MIPS errata"
	depends on RISCV_ALTERNATIVE
	help
	  All MIPS errata Kconfig depend on this Kconfig. Disabling
	  this Kconfig will disable all MIPS errata. Please say "Y"
	  here if your platform uses MIPS CPU cores.

	  Otherwise, please say "N" here to avoid unnecessary overhead.

config ERRATA_MIPS_P8700_PAUSE_OPCODE
	bool "Fix the PAUSE Opcode for MIPS P8700"
	depends on ERRATA_MIPS && 64BIT
	default n
	help
	   The RISCV MIPS P8700 uses a different opcode for PAUSE.
	   It is a 'hint' encoding of the SLLI instruction,
	   with rd=0, rs1=0 and imm=5. It will behave as a NOP
	   instruction if no additional behavior beyond that of
	   SLLI is implemented.

	   If you are not using the P8700 processor, say n.

config ERRATA_SIFIVE
	bool "SiFive errata"
	depends on RISCV_ALTERNATIVE
	help
	  All SiFive errata Kconfig depend on this Kconfig. Disabling
	  this Kconfig will disable all SiFive errata. Please say "Y"
	  here if your platform uses SiFive CPU cores.

	  Otherwise, please say "N" here to avoid unnecessary overhead.

config ERRATA_SIFIVE_CIP_453
	bool "Apply SiFive errata CIP-453"
	depends on ERRATA_SIFIVE && 64BIT
	default y
	help
	  This will apply the SiFive CIP-453 errata to add sign extension
	  to the $badaddr when exception type is instruction page fault
	  and instruction access fault.

	  If you don't know what to do here, say "Y".

config ERRATA_SIFIVE_CIP_1200
	bool "Apply SiFive errata CIP-1200"
	depends on ERRATA_SIFIVE && 64BIT

Annotation

Implementation Notes