arch/riscv/kernel/head.h
Source file repositories/reference/linux-study-clean/arch/riscv/kernel/head.h
File Facts
- System
- Linux kernel
- Corpus path
arch/riscv/kernel/head.h- Extension
.h- Size
- 416 bytes
- Lines
- 21
- Domain
- Architecture Layer
- Bucket
- arch/riscv
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
Dependency Surface
linux/linkage.hlinux/init.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef __ASM_HEAD_H
#define __ASM_HEAD_H
#include <linux/linkage.h>
#include <linux/init.h>
extern atomic_t hart_lottery;
asmlinkage void __init setup_vm(uintptr_t dtb_pa);
#ifdef CONFIG_RISCV_BOOT_SPINWAIT
extern void *__cpu_spinwait_stack_pointer[];
extern void *__cpu_spinwait_task_pointer[];
#endif
#endif /* __ASM_HEAD_H */
Annotation
- Immediate include surface: `linux/linkage.h`, `linux/init.h`.
- Atlas domain: Architecture Layer / arch/riscv.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.