arch/riscv/kvm/vcpu_onereg.c
Source file repositories/reference/linux-study-clean/arch/riscv/kvm/vcpu_onereg.c
File Facts
- System
- Linux kernel
- Corpus path
arch/riscv/kvm/vcpu_onereg.c- Extension
.c- Size
- 26824 bytes
- Lines
- 1077
- Domain
- Architecture Layer
- Bucket
- arch/riscv
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Touches user memory; correctness depends on fault-safe copying and privilege boundary handling.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/bitops.hlinux/errno.hlinux/err.hlinux/nospec.hlinux/uaccess.hlinux/kvm_host.hasm/cacheflush.hasm/cpufeature.hasm/kvm_isa.hasm/kvm_vcpu_vector.h
Detected Declarations
function Copyrightfunction kvm_riscv_vcpu_get_reg_configfunction kvm_riscv_vcpu_set_reg_configfunction kvm_riscv_vcpu_get_reg_corefunction kvm_riscv_vcpu_set_reg_corefunction kvm_riscv_vcpu_general_get_csrfunction kvm_riscv_vcpu_general_set_csrfunction kvm_riscv_vcpu_smstateen_set_csrfunction kvm_riscv_vcpu_smstateen_get_csrfunction kvm_riscv_vcpu_get_reg_csrfunction kvm_riscv_vcpu_set_reg_csrfunction riscv_vcpu_get_isa_ext_singlefunction riscv_vcpu_set_isa_ext_singlefunction riscv_vcpu_get_isa_ext_multifunction riscv_vcpu_set_isa_ext_multifunction for_each_set_bitfunction kvm_riscv_vcpu_get_reg_isa_extfunction kvm_riscv_vcpu_set_reg_isa_extfunction copy_config_reg_indicesfunction num_config_regsfunction num_core_regsfunction copy_core_reg_indicesfunction num_csr_regsfunction copy_csr_reg_indicesfunction num_timer_regsfunction copy_timer_reg_indicesfunction num_fp_f_regsfunction copy_fp_f_reg_indicesfunction num_fp_d_regsfunction copy_fp_d_reg_indicesfunction copy_isa_ext_reg_indicesfunction num_isa_ext_regsfunction num_sbi_ext_regsfunction num_sbi_regsfunction num_vector_regsfunction copy_vector_reg_indicesfunction kvm_riscv_vcpu_num_regsfunction kvm_riscv_vcpu_copy_reg_indicesfunction kvm_riscv_vcpu_set_regfunction kvm_riscv_vcpu_get_reg
Annotated Snippet
if (!vcpu->arch.ran_atleast_once) {
/* Ignore the enable/disable request for certain extensions */
for (i = 0; i < RISCV_ISA_EXT_BASE; i++) {
isa_ext = kvm_riscv_base2isa_ext(i);
if (isa_ext >= KVM_RISCV_ISA_EXT_MAX) {
reg_val &= ~BIT(i);
continue;
}
if (!kvm_riscv_isa_enable_allowed(isa_ext))
if (reg_val & BIT(i))
reg_val &= ~BIT(i);
if (!kvm_riscv_isa_disable_allowed(isa_ext))
if (!(reg_val & BIT(i)))
reg_val |= BIT(i);
}
reg_val &= riscv_isa_extension_base(NULL);
/* Do not modify anything beyond single letter extensions */
reg_val = (vcpu->arch.isa[0] & ~KVM_RISCV_BASE_ISA_MASK) |
(reg_val & KVM_RISCV_BASE_ISA_MASK);
vcpu->arch.isa[0] = reg_val;
kvm_riscv_vcpu_fp_reset(vcpu);
} else {
return -EBUSY;
}
break;
case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
if (kvm_riscv_isa_check_host(ZICBOM))
return -ENOENT;
if (reg_val != riscv_cbom_block_size)
return -EINVAL;
break;
case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size):
if (kvm_riscv_isa_check_host(ZICBOZ))
return -ENOENT;
if (reg_val != riscv_cboz_block_size)
return -EINVAL;
break;
case KVM_REG_RISCV_CONFIG_REG(zicbop_block_size):
if (kvm_riscv_isa_check_host(ZICBOP))
return -ENOENT;
if (reg_val != riscv_cbop_block_size)
return -EINVAL;
break;
case KVM_REG_RISCV_CONFIG_REG(mvendorid):
if (reg_val == vcpu->arch.mvendorid)
break;
if (!vcpu->arch.ran_atleast_once)
vcpu->arch.mvendorid = reg_val;
else
return -EBUSY;
break;
case KVM_REG_RISCV_CONFIG_REG(marchid):
if (reg_val == vcpu->arch.marchid)
break;
if (!vcpu->arch.ran_atleast_once)
vcpu->arch.marchid = reg_val;
else
return -EBUSY;
break;
case KVM_REG_RISCV_CONFIG_REG(mimpid):
if (reg_val == vcpu->arch.mimpid)
break;
if (!vcpu->arch.ran_atleast_once)
vcpu->arch.mimpid = reg_val;
else
return -EBUSY;
break;
case KVM_REG_RISCV_CONFIG_REG(satp_mode):
if (reg_val != (satp_mode >> SATP_MODE_SHIFT))
return -EINVAL;
break;
default:
return -ENOENT;
}
return 0;
}
static int kvm_riscv_vcpu_get_reg_core(struct kvm_vcpu *vcpu,
const struct kvm_one_reg *reg)
{
struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;
unsigned long __user *uaddr =
(unsigned long __user *)(unsigned long)reg->addr;
unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
KVM_REG_SIZE_MASK |
KVM_REG_RISCV_CORE);
unsigned long regs_max = sizeof(struct kvm_riscv_core) / sizeof(unsigned long);
unsigned long reg_val;
Annotation
- Immediate include surface: `linux/bitops.h`, `linux/errno.h`, `linux/err.h`, `linux/nospec.h`, `linux/uaccess.h`, `linux/kvm_host.h`, `asm/cacheflush.h`, `asm/cpufeature.h`.
- Detected declarations: `function Copyright`, `function kvm_riscv_vcpu_get_reg_config`, `function kvm_riscv_vcpu_set_reg_config`, `function kvm_riscv_vcpu_get_reg_core`, `function kvm_riscv_vcpu_set_reg_core`, `function kvm_riscv_vcpu_general_get_csr`, `function kvm_riscv_vcpu_general_set_csr`, `function kvm_riscv_vcpu_smstateen_set_csr`, `function kvm_riscv_vcpu_smstateen_get_csr`, `function kvm_riscv_vcpu_get_reg_csr`.
- Atlas domain: Architecture Layer / arch/riscv.
- Implementation status: source implementation candidate.
- This snippet crosses the user/kernel memory boundary; validate fault handling and access checks before translating the pattern.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.