arch/riscv/mm/tlbflush.c
Source file repositories/reference/linux-study-clean/arch/riscv/mm/tlbflush.c
File Facts
- System
- Linux kernel
- Corpus path
arch/riscv/mm/tlbflush.c- Extension
.c- Size
- 6117 bytes
- Lines
- 243
- Domain
- Architecture Layer
- Bucket
- arch/riscv
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/mm.hlinux/smp.hlinux/sched.hlinux/hugetlb.hlinux/mmu_notifier.hasm/sbi.hasm/mmu_context.hasm/cpufeature.h
Detected Declarations
struct flush_tlb_range_datafunction local_sfence_inval_irfunction local_sfence_w_invalfunction local_sinval_vmafunction local_flush_tlb_range_threshold_asidfunction local_flush_tlb_range_asidfunction local_flush_tlb_kernel_rangefunction __ipi_flush_tlb_allfunction flush_tlb_allfunction __ipi_flush_tlb_range_asidfunction get_mm_asidfunction __flush_tlb_rangefunction flush_tlb_mmfunction flush_tlb_mm_rangefunction flush_tlb_pagefunction flush_tlb_rangefunction flush_tlb_kernel_rangefunction flush_pmd_tlb_rangefunction flush_pud_tlb_rangefunction arch_tlbbatch_should_deferfunction arch_tlbbatch_add_pendingfunction arch_tlbbatch_flush
Annotated Snippet
struct flush_tlb_range_data {
unsigned long asid;
unsigned long start;
unsigned long size;
unsigned long stride;
};
static void __ipi_flush_tlb_range_asid(void *info)
{
struct flush_tlb_range_data *d = info;
local_flush_tlb_range_asid(d->start, d->size, d->stride, d->asid);
}
static inline unsigned long get_mm_asid(struct mm_struct *mm)
{
return mm ? cntx2asid(atomic_long_read(&mm->context.id)) : FLUSH_TLB_NO_ASID;
}
static void __flush_tlb_range(struct mm_struct *mm,
const struct cpumask *cmask,
unsigned long start, unsigned long size,
unsigned long stride)
{
unsigned long asid = get_mm_asid(mm);
unsigned int cpu;
if (cpumask_empty(cmask))
return;
cpu = get_cpu();
/* Check if the TLB flush needs to be sent to other CPUs. */
if (cpumask_any_but(cmask, cpu) >= nr_cpu_ids) {
local_flush_tlb_range_asid(start, size, stride, asid);
} else if (riscv_use_sbi_for_rfence()) {
sbi_remote_sfence_vma_asid(cmask, start, size, asid);
} else {
struct flush_tlb_range_data ftd;
ftd.asid = asid;
ftd.start = start;
ftd.size = size;
ftd.stride = stride;
on_each_cpu_mask(cmask, __ipi_flush_tlb_range_asid, &ftd, 1);
}
put_cpu();
if (mm)
mmu_notifier_arch_invalidate_secondary_tlbs(mm, start, start + size);
}
void flush_tlb_mm(struct mm_struct *mm)
{
__flush_tlb_range(mm, mm_cpumask(mm), 0, FLUSH_TLB_MAX_SIZE, PAGE_SIZE);
}
void flush_tlb_mm_range(struct mm_struct *mm,
unsigned long start, unsigned long end,
unsigned int page_size)
{
__flush_tlb_range(mm, mm_cpumask(mm), start, end - start, page_size);
}
void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
{
__flush_tlb_range(vma->vm_mm, mm_cpumask(vma->vm_mm),
addr, PAGE_SIZE, PAGE_SIZE);
}
void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
unsigned long end)
{
unsigned long stride_size;
if (!is_vm_hugetlb_page(vma)) {
stride_size = PAGE_SIZE;
} else {
stride_size = huge_page_size(hstate_vma(vma));
/*
* As stated in the privileged specification, every PTE in a
* NAPOT region must be invalidated, so reset the stride in that
* case.
*/
if (has_svnapot()) {
if (stride_size >= PGDIR_SIZE)
stride_size = PGDIR_SIZE;
else if (stride_size >= P4D_SIZE)
Annotation
- Immediate include surface: `linux/mm.h`, `linux/smp.h`, `linux/sched.h`, `linux/hugetlb.h`, `linux/mmu_notifier.h`, `asm/sbi.h`, `asm/mmu_context.h`, `asm/cpufeature.h`.
- Detected declarations: `struct flush_tlb_range_data`, `function local_sfence_inval_ir`, `function local_sfence_w_inval`, `function local_sinval_vma`, `function local_flush_tlb_range_threshold_asid`, `function local_flush_tlb_range_asid`, `function local_flush_tlb_kernel_range`, `function __ipi_flush_tlb_all`, `function flush_tlb_all`, `function __ipi_flush_tlb_range_asid`.
- Atlas domain: Architecture Layer / arch/riscv.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.