arch/s390/include/asm/fpu-insn-asm.h

Source file repositories/reference/linux-study-clean/arch/s390/include/asm/fpu-insn-asm.h

File Facts

System
Linux kernel
Corpus path
arch/s390/include/asm/fpu-insn-asm.h
Extension
.h
Size
13462 bytes
Lines
583
Domain
Architecture Layer
Bucket
arch/s390
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __ASM_S390_FPU_INSN_ASM_H
#define __ASM_S390_FPU_INSN_ASM_H

#ifndef __ASM_S390_FPU_INSN_H
#error only <asm/fpu-insn.h> can be included directly
#endif

#include <asm/insn-common-asm.h>

#ifdef __ASSEMBLER__

/* RXB - Compute most significant bit used vector registers
 *
 * @rxb:	Operand to store computed RXB value
 * @v1:		Vector register designated operand whose MSB is stored in
 *		RXB bit 0 (instruction bit 36) and whose remaining bits
 *		are stored in instruction bits 8-11.
 * @v2:		Vector register designated operand whose MSB is stored in
 *		RXB bit 1 (instruction bit 37) and whose remaining bits
 *		are stored in instruction bits 12-15.
 * @v3:		Vector register designated operand whose MSB is stored in
 *		RXB bit 2 (instruction bit 38) and whose remaining bits
 *		are stored in instruction bits 16-19.
 * @v4:		Vector register designated operand whose MSB is stored in
 *		RXB bit 3 (instruction bit 39) and whose remaining bits
 *		are stored in instruction bits 32-35.
 *
 * Note: In most vector instruction formats [1] V1, V2, V3, and V4 directly
 * correspond to @v1, @v2, @v3, and @v4. But there are exceptions, such as but
 * not limited to the vector instruction formats VRR-g, VRR-h, VRS-a, VRS-d,
 * and VSI.
 *
 * [1] IBM z/Architecture Principles of Operation, chapter "Program
 * Execution, section "Instructions", subsection "Instruction Formats".
 */
.macro	RXB	rxb v1 v2=0 v3=0 v4=0
	\rxb = 0
	.if \v1 & 0x10
		\rxb = \rxb | 0x08
	.endif
	.if \v2 & 0x10
		\rxb = \rxb | 0x04
	.endif
	.if \v3 & 0x10
		\rxb = \rxb | 0x02
	.endif
	.if \v4 & 0x10
		\rxb = \rxb | 0x01
	.endif
.endm

/* MRXB - Generate Element Size Control and RXB value
 *
 * @m:		Element size control
 * @v1:		First vector register designated operand (for RXB)
 * @v2:		Second vector register designated operand (for RXB)
 * @v3:		Third vector register designated operand (for RXB)
 * @v4:		Fourth vector register designated operand (for RXB)
 *
 * Note: For @v1, @v2, @v3, and @v4 also refer to the RXB macro
 * description for further details.
 */
.macro	MRXB	m v1 v2=0 v3=0 v4=0
	rxb = 0
	RXB	rxb, \v1, \v2, \v3, \v4
	.byte	(\m << 4) | rxb
.endm

/* MRXBOPC - Generate Element Size Control, RXB, and final Opcode fields
 *
 * @m:		Element size control
 * @opc:	Opcode
 * @v1:		First vector register designated operand (for RXB)
 * @v2:		Second vector register designated operand (for RXB)
 * @v3:		Third vector register designated operand (for RXB)
 * @v4:		Fourth vector register designated operand (for RXB)
 *
 * Note: For @v1, @v2, @v3, and @v4 also refer to the RXB macro
 * description for further details.
 */
.macro	MRXBOPC	m opc v1 v2=0 v3=0 v4=0
	MRXB	\m, \v1, \v2, \v3, \v4
	.byte	\opc
.endm

/* Vector support instructions */

/* VECTOR GENERATE BYTE MASK */
.macro	VGBM	vr imm2
	VX_NUM	v1, \vr

Annotation

Implementation Notes