arch/s390/include/asm/pci_clp.h
Source file repositories/reference/linux-study-clean/arch/s390/include/asm/pci_clp.h
File Facts
- System
- Linux kernel
- Corpus path
arch/s390/include/asm/pci_clp.h- Extension
.h- Size
- 5544 bytes
- Lines
- 226
- Domain
- Architecture Layer
- Bucket
- arch/s390
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
asm/clp.h
Detected Declarations
struct clp_fh_list_entrystruct clp_rsp_slpc_pcistruct clp_req_list_pcistruct clp_rsp_list_pcistruct mio_infostruct clp_req_query_pcistruct clp_rsp_query_pcistruct clp_req_query_pci_grpstruct clp_rsp_query_pci_grpstruct clp_req_set_pcistruct clp_rsp_set_pcistruct clp_req_rsp_slpc_pcistruct clp_req_rsp_list_pcistruct clp_req_rsp_set_pcistruct clp_req_rsp_query_pcistruct clp_req_rsp_query_pci_grp
Annotated Snippet
struct clp_fh_list_entry {
u16 device_id;
u16 vendor_id;
u32 config_state : 1;
u32 : 31;
u32 fid; /* PCI function id */
u32 fh; /* PCI function handle */
} __packed;
#define CLP_RC_SETPCIFN_FH 0x0101 /* Invalid PCI fn handle */
#define CLP_RC_SETPCIFN_FHOP 0x0102 /* Fn handle not valid for op */
#define CLP_RC_SETPCIFN_DMAAS 0x0103 /* Invalid DMA addr space */
#define CLP_RC_SETPCIFN_RES 0x0104 /* Insufficient resources */
#define CLP_RC_SETPCIFN_ALRDY 0x0105 /* Fn already in requested state */
#define CLP_RC_SETPCIFN_ERR 0x0106 /* Fn in permanent error state */
#define CLP_RC_SETPCIFN_RECPND 0x0107 /* Error recovery pending */
#define CLP_RC_SETPCIFN_BUSY 0x0108 /* Fn busy */
#define CLP_RC_LISTPCI_BADRT 0x010a /* Resume token not recognized */
#define CLP_RC_QUERYPCIFG_PFGID 0x010b /* Unrecognized PFGID */
/* request or response block header length */
#define LIST_PCI_HDR_LEN 32
/* Number of function handles fitting in response block */
#define CLP_FH_LIST_NR_ENTRIES \
((CLP_BLK_SIZE - 2 * LIST_PCI_HDR_LEN) \
/ sizeof(struct clp_fh_list_entry))
#define CLP_SET_ENABLE_PCI_FN 0 /* Yes, 0 enables it */
#define CLP_SET_DISABLE_PCI_FN 1 /* Yes, 1 disables it */
#define CLP_SET_ENABLE_MIO 2
#define CLP_SET_DISABLE_MIO 3
#define CLP_UTIL_STR_LEN 64
#define CLP_PFIP_NR_SEGMENTS 4
/* PCI function type numbers */
#define PCI_FUNC_TYPE_ISM 0x5 /* ISM device */
extern bool zpci_unique_uid;
struct clp_rsp_slpc_pci {
struct clp_rsp_hdr hdr;
u32 reserved2[4];
u32 lpif[8];
u32 reserved3[4];
u32 vwb : 1;
u32 : 1;
u32 mio_wb : 6;
u32 : 24;
u32 reserved5[3];
u32 lpic[8];
} __packed;
/* List PCI functions request */
struct clp_req_list_pci {
struct clp_req_hdr hdr;
u64 resume_token;
u64 reserved2;
} __packed;
/* List PCI functions response */
struct clp_rsp_list_pci {
struct clp_rsp_hdr hdr;
u64 resume_token;
u32 reserved2;
u16 max_fn;
u8 : 7;
u8 uid_checking : 1;
u8 entry_size;
struct clp_fh_list_entry fh_list[CLP_FH_LIST_NR_ENTRIES];
} __packed;
struct mio_info {
u32 valid : 6;
u32 : 26;
u32 : 32;
struct {
u64 wb;
u64 wt;
} addr[PCI_STD_NUM_BARS];
u32 reserved[6];
} __packed;
/* Query PCI function request */
struct clp_req_query_pci {
struct clp_req_hdr hdr;
u32 fh; /* function handle */
u32 reserved2;
u64 reserved3;
Annotation
- Immediate include surface: `asm/clp.h`.
- Detected declarations: `struct clp_fh_list_entry`, `struct clp_rsp_slpc_pci`, `struct clp_req_list_pci`, `struct clp_rsp_list_pci`, `struct mio_info`, `struct clp_req_query_pci`, `struct clp_rsp_query_pci`, `struct clp_req_query_pci_grp`, `struct clp_rsp_query_pci_grp`, `struct clp_req_set_pci`.
- Atlas domain: Architecture Layer / arch/s390.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.