arch/sh/boards/board-apsh4ad0a.c
Source file repositories/reference/linux-study-clean/arch/sh/boards/board-apsh4ad0a.c
File Facts
- System
- Linux kernel
- Corpus path
arch/sh/boards/board-apsh4ad0a.c- Extension
.c- Size
- 3267 bytes
- Lines
- 133
- Domain
- Architecture Layer
- Bucket
- arch/sh
- Inferred role
- Architecture Layer: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/init.hlinux/platform_device.hlinux/io.hlinux/regulator/fixed.hlinux/regulator/machine.hlinux/smsc911x.hlinux/irq.hlinux/clk.hasm/machvec.hlinux/sizes.h
Detected Declarations
function apsh4ad0a_devices_setupfunction apsh4ad0a_mode_pinsfunction apsh4ad0a_clk_initfunction apsh4ad0a_setupfunction apsh4ad0a_init_irqmodule init apsh4ad0a_devices_setup
Annotated Snippet
device_initcall(apsh4ad0a_devices_setup);
static int apsh4ad0a_mode_pins(void)
{
int value = 0;
/* These are the factory default settings of SW1 and SW2.
* If you change these dip switches then you will need to
* adjust the values below as well.
*/
value |= MODE_PIN0; /* Clock Mode 3 */
value |= MODE_PIN1;
value &= ~MODE_PIN2;
value &= ~MODE_PIN3;
value &= ~MODE_PIN4; /* 16-bit Area0 bus width */
value |= MODE_PIN5;
value |= MODE_PIN6;
value |= MODE_PIN7; /* Normal mode */
value |= MODE_PIN8; /* Little Endian */
value |= MODE_PIN9; /* Crystal resonator */
value &= ~MODE_PIN10; /* 29-bit address mode */
value &= ~MODE_PIN11; /* PCI-E Root port */
value &= ~MODE_PIN12; /* 4 lane + 1 lane */
value |= MODE_PIN13; /* AUD Enable */
value &= ~MODE_PIN14; /* Normal Operation */
return value;
}
static int apsh4ad0a_clk_init(void)
{
struct clk *clk;
int ret;
clk = clk_get(NULL, "extal");
if (IS_ERR(clk))
return PTR_ERR(clk);
ret = clk_set_rate(clk, 33333000);
clk_put(clk);
return ret;
}
/* Initialize the board */
static void __init apsh4ad0a_setup(char **cmdline_p)
{
pr_info("Alpha Project AP-SH4AD-0A support:\n");
}
static void __init apsh4ad0a_init_irq(void)
{
plat_irq_setup_pins(IRQ_MODE_IRQ3210);
}
/*
* The Machine Vector
*/
static struct sh_machine_vector mv_apsh4ad0a __initmv = {
.mv_name = "AP-SH4AD-0A",
.mv_setup = apsh4ad0a_setup,
.mv_mode_pins = apsh4ad0a_mode_pins,
.mv_clk_init = apsh4ad0a_clk_init,
.mv_init_irq = apsh4ad0a_init_irq,
};
Annotation
- Immediate include surface: `linux/init.h`, `linux/platform_device.h`, `linux/io.h`, `linux/regulator/fixed.h`, `linux/regulator/machine.h`, `linux/smsc911x.h`, `linux/irq.h`, `linux/clk.h`.
- Detected declarations: `function apsh4ad0a_devices_setup`, `function apsh4ad0a_mode_pins`, `function apsh4ad0a_clk_init`, `function apsh4ad0a_setup`, `function apsh4ad0a_init_irq`, `module init apsh4ad0a_devices_setup`.
- Atlas domain: Architecture Layer / arch/sh.
- Implementation status: integration implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.