arch/sh/boards/board-sh7785lcr.c

Source file repositories/reference/linux-study-clean/arch/sh/boards/board-sh7785lcr.c

File Facts

System
Linux kernel
Corpus path
arch/sh/boards/board-sh7785lcr.c
Extension
.c
Size
8707 bytes
Lines
385
Domain
Architecture Layer
Bucket
arch/sh
Inferred role
Architecture Layer: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

device_initcall(sh7785lcr_devices_setup);

/* Initialize IRQ setting */
static void __init init_sh7785lcr_IRQ(void)
{
	plat_irq_setup_pins(IRQ_MODE_IRQ7654);
	plat_irq_setup_pins(IRQ_MODE_IRQ3210);
}

static int sh7785lcr_clk_init(void)
{
	struct clk *clk;
	int ret;

	clk = clk_get(NULL, "extal");
	if (IS_ERR(clk))
		return PTR_ERR(clk);
	ret = clk_set_rate(clk, 33333333);
	clk_put(clk);

	return ret;
}

static void sh7785lcr_power_off(void)
{
	unsigned char *p;

	p = ioremap(PLD_POFCR, PLD_POFCR + 1);
	if (!p) {
		printk(KERN_ERR "%s: ioremap error.\n", __func__);
		return;
	}
	*p = 0x01;
	iounmap(p);
	set_bl_bit();
	while (1)
		cpu_relax();
}

/* Initialize the board */
static void __init sh7785lcr_setup(char **cmdline_p)
{
	void __iomem *sm501_reg;

	printk(KERN_INFO "Renesas Technology Corp. R0P7785LC0011RL support.\n");

	pm_power_off = sh7785lcr_power_off;

	/* sm501 DRAM configuration */
	sm501_reg = ioremap(SM107_REG_ADDR, SM501_DRAM_CONTROL);
	if (!sm501_reg) {
		printk(KERN_ERR "%s: ioremap error.\n", __func__);
		return;
	}

	writel(0x000307c2, sm501_reg + SM501_DRAM_CONTROL);
	iounmap(sm501_reg);
}

/* Return the board specific boot mode pin configuration */
static int sh7785lcr_mode_pins(void)
{
	int value = 0;

	/* These are the factory default settings of S1 and S2.
	 * If you change these dip switches then you will need to
	 * adjust the values below as well.
	 */
	value |= MODE_PIN4; /* Clock Mode 16 */
	value |= MODE_PIN5; /* 32-bit Area0 bus width */
	value |= MODE_PIN6; /* 32-bit Area0 bus width */
	value |= MODE_PIN7; /* Area 0 SRAM interface [fixed] */
	value |= MODE_PIN8; /* Little Endian */
	value |= MODE_PIN9; /* Master Mode */
	value |= MODE_PIN14; /* No PLL step-up */

	return value;
}

/*
 * The Machine Vector
 */
static struct sh_machine_vector mv_sh7785lcr __initmv = {
	.mv_name		= "SH7785LCR",
	.mv_setup		= sh7785lcr_setup,
	.mv_clk_init		= sh7785lcr_clk_init,
	.mv_init_irq		= init_sh7785lcr_IRQ,
	.mv_mode_pins		= sh7785lcr_mode_pins,
};

Annotation

Implementation Notes