arch/sh/boot/compressed/head_64.S

Source file repositories/reference/linux-study-clean/arch/sh/boot/compressed/head_64.S

File Facts

System
Linux kernel
Corpus path
arch/sh/boot/compressed/head_64.S
Extension
.S
Size
4021 bytes
Lines
160
Domain
Architecture Layer
Bucket
arch/sh
Inferred role
Architecture Layer: arch/sh
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#include <asm/cache.h>
#include <asm/tlb.h>
#include <cpu/mmu_context.h>
#include <cpu/registers.h>

/*
 * Fixed TLB entries to identity map the beginning of RAM
 */
#define MMUIR_TEXT_H	0x0000000000000003 | CONFIG_MEMORY_START
			/* Enabled, Shared, ASID 0, Eff. Add. 0xA0000000 */
#define MMUIR_TEXT_L	0x000000000000009a | CONFIG_MEMORY_START
			/* 512 Mb, Cacheable (Write-back), execute, Not User, Ph. Add. */

#define MMUDR_CACHED_H	0x0000000000000003 | CONFIG_MEMORY_START
			/* Enabled, Shared, ASID 0, Eff. Add. 0xA0000000 */
#define MMUDR_CACHED_L	0x000000000000015a | CONFIG_MEMORY_START
			/* 512 Mb, Cacheable (Write-back), read/write, Not User, Ph. Add. */

#define	ICCR0_INIT_VAL	ICCR0_ON | ICCR0_ICI		/* ICE + ICI */
#define	ICCR1_INIT_VAL	ICCR1_NOLOCK			/* No locking */

#define	OCCR0_INIT_VAL	OCCR0_ON | OCCR0_OCI | OCCR0_WB	/* OCE + OCI + WB */
#define	OCCR1_INIT_VAL	OCCR1_NOLOCK			/* No locking */

	.text

	.global	startup
startup:
	/*
	 * Prevent speculative fetch on device memory due to
	 * uninitialized target registers.
	 * This must be executed before the first branch.
	 */
	ptabs/u	r63, tr0
	ptabs/u	r63, tr1
	ptabs/u	r63, tr2
	ptabs/u	r63, tr3
	ptabs/u	r63, tr4
	ptabs/u	r63, tr5
	ptabs/u	r63, tr6
	ptabs/u	r63, tr7
	synci

	/*
	 * Set initial TLB entries for cached and uncached regions.
	 * Note: PTA/BLINK is PIC code, PTABS/BLINK isn't !
	 */
	/* Clear ITLBs */
	pta	1f, tr1
	movi	ITLB_FIXED, r21
	movi	ITLB_LAST_VAR_UNRESTRICTED+TLB_STEP, r22
1:	putcfg	r21, 0, r63		/* Clear MMUIR[n].PTEH.V */
	addi	r21, TLB_STEP, r21
        bne	r21, r22, tr1

	/* Clear DTLBs */
	pta	1f, tr1
	movi	DTLB_FIXED, r21
	movi	DTLB_LAST_VAR_UNRESTRICTED+TLB_STEP, r22
1:	putcfg	r21, 0, r63		/* Clear MMUDR[n].PTEH.V */
	addi	r21, TLB_STEP, r21
        bne	r21, r22, tr1

	/* Map one big (512Mb) page for ITLB */
	movi	ITLB_FIXED, r21
	movi	MMUIR_TEXT_L, r22	/* PTEL first */
	putcfg	r21, 1, r22		/* Set MMUIR[0].PTEL */
	movi	MMUIR_TEXT_H, r22	/* PTEH last */
	putcfg	r21, 0, r22		/* Set MMUIR[0].PTEH */

Annotation

Implementation Notes