arch/sh/drivers/pci/pcie-sh7786.h

Source file repositories/reference/linux-study-clean/arch/sh/drivers/pci/pcie-sh7786.h

File Facts

System
Linux kernel
Corpus path
arch/sh/drivers/pci/pcie-sh7786.h
Extension
.h
Size
25785 bytes
Lines
578
Domain
Architecture Layer
Bucket
arch/sh
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __PCI_SH7786_H
#define __PCI_SH7786_H

/* PCIe bus-0(x4) on SH7786 */			// Rev1.171
#define SH4A_PCIE_SPW_BASE	0xFE000000	/* spw config address for controller 0 */
#define SH4A_PCIE_SPW_BASE1	0xFE200000	/* spw config address for controller 1 (Rev1.14)*/
#define SH4A_PCIE_SPW_BASE2	0xFCC00000	/* spw config address for controller 2 (Rev1.171)*/
#define SH4A_PCIE_SPW_BASE_LEN	0x00080000

#define SH4A_PCI_CNFG_BASE	0xFE040000	/* pci config address for controller 0 */
#define SH4A_PCI_CNFG_BASE1	0xFE240000	/* pci config address for controller 1 (Rev1.14)*/
#define SH4A_PCI_CNFG_BASE2	0xFCC40000	/* pci config address for controller 2 (Rev1.171)*/
#define SH4A_PCI_CNFG_BASE_LEN	0x00040000

#define SH4A_PCIPIO_ADDR_OFFSET	0x000001c0	/* offset to pci config_address */
#define SH4A_PCIPIO_DATA_OFFSET	0x00000220	/* offset to pci config_data */

/*
 * for PEX8111(Max Payload Size=128B,PCIIO_SIZE=64K),
 * for other(Max Payload Size=4096B,PCIIO_SIZE=8M)
 */

/* PCI0: PCI memory target transfer 32-bit address translation value(Rev1.11T)*/
#define SH4A_PCIBMSTR_TRANSLATION	0x20000000

/*	SPVCR0		*/
#define	SH4A_PCIEVCR0		(0x000000)	/* R - 0x0000 0000 32 */
#define		BITS_TOP_MB	(24)
#define		MASK_TOP_MB	(0xff<<BITS_TOP_MB)
#define		BITS_BOT_MB	(16)
#define		MASK_BOT_MB	(0xff<<BITS_BOT_MB)
#define		BITS_VC_ID	(0)
#define		MASK_VC_ID	(0xffff<<BITS_VC_ID)

/*	SPVCR1		*/
#define	SH4A_PCIEVCR1		(0x000004)	/* R - 0x0000 0000 32*/
#define		BITS_BADOPC	(5)		/* 5 BADOPC 0 R/W */
#define		MASK_BADOPC	(1<<BITS_BADOPC)
#define		BITS_BADDEST	(4)		/*4 BADDEST 0 R/W  */
#define		MASK_BADDEST	(1<<BITS_BADDEST)
#define		BITS_UNSOLRESP	(3)		/* 3 UNSOLRESP 0 R/W  */
#define		MASK_UNSOLRESP	(1<<BITS_UNSOLRESP)
#define		BITS_ERRSNT	(1)		/* 1 ERRSNT 0 */
#define		MASK_ERRSNT	(1<<BITS_ERRSNT)
#define		BITS_ERRRCV	(0)		/* 0 ERRRCV 0 */
#define		MASK_ERRRCV	(1<<BITS_ERRRCV)

/*	PCIEENBLR	 */
#define	SH4A_PCIEENBLR		(0x000008)	/* R/W - 0x0000 0001 32 */

/*	PCIEECR		*/
#define	SH4A_PCIEECR		(0x00000C)	/* R/W - 0x0000 0000 32 */
#define		BITS_ENBL	(0)	/* 0 ENBL 0 R/W */
#define		MASK_ENBL	(1<<BITS_ENBL)

/*	PCIEPAR		*/
#define	SH4A_PCIEPAR		(0x000010)	/* R/W - 0x0000 0000 32 */
#define		BITS_BN		(24)
#define		MASK_BN		(0xff<<BITS_BN)
#define		BITS_DN		(19)
#define		MASK_DN		(0x1f<<BITS_DN)
#define		BITS_FN		(16)
#define		MASK_FN		(0x7<<BITS_FN)
#define		BITS_EREGNO	(8)
#define		MASK_EREGNO	(0xff<<BITS_EREGNO)
#define		BITS_REGNO	(2)
#define		MASK_REGNO	(0x3f<<BITS_REGNO)

/*	PCIEPCTLR	*/
#define	SH4A_PCIEPCTLR		(0x000018)	/* R/W - 0x0000 0000 32 */
#define		BITS_CCIE	(31)	/*  31 CCIE */
#define		MASK_CCIE	(1<<BITS_CCIE)
#define		BITS_TYPE	(8)
#define		MASK_TYPE	(1<<BITS_TYPE)
#define		BITS_C_VC	(0)
#define		MASK_C_VC	(1<<BITS_C_VC)

/*	PCIEPDR		*/
#define	SH4A_PCIEPDR		(0x000020)	/* R/W - 0x0000 0000 32 */
#define		BITS_PDR	(0)
#define		MASK_PDR	(0xffffffff<<BITS_PDR)

/*	PCIEMSGALR	*/
#define	SH4A_PCIEMSGALR		(0x000030)	/* R/W - 0x0000 0000 32 */
#define		BITS_MSGADRL	(0)
#define		MASK_MSGADRL	(0xffffffff<<BITS_MSGADRL)

/*	PCIEMSGAHR	*/
#define	SH4A_PCIEMSGAHR		(0x000034)	/* R/W - 0x0000 0000 32 */
#define		BITS_MSGADRH	(0)

Annotation

Implementation Notes