arch/sh/include/asm/dmabrg.h
Source file repositories/reference/linux-study-clean/arch/sh/include/asm/dmabrg.h
File Facts
- System
- Linux kernel
- Corpus path
arch/sh/include/asm/dmabrg.h- Extension
.h- Size
- 536 bytes
- Lines
- 25
- Domain
- Architecture Layer
- Bucket
- arch/sh
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _DMABRG_H_
#define _DMABRG_H_
/* IRQ sources */
#define DMABRGIRQ_USBDMA 0
#define DMABRGIRQ_USBDMAERR 1
#define DMABRGIRQ_A0TXF 2
#define DMABRGIRQ_A0TXH 3
#define DMABRGIRQ_A0RXF 4
#define DMABRGIRQ_A0RXH 5
#define DMABRGIRQ_A1TXF 6
#define DMABRGIRQ_A1TXH 7
#define DMABRGIRQ_A1RXF 8
#define DMABRGIRQ_A1RXH 9
extern int dmabrg_request_irq(unsigned int, void(*)(void *), void *);
extern void dmabrg_free_irq(unsigned int);
#endif
Annotation
- Atlas domain: Architecture Layer / arch/sh.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.