arch/sh/include/asm/hd64461.h

Source file repositories/reference/linux-study-clean/arch/sh/include/asm/hd64461.h

File Facts

System
Linux kernel
Corpus path
arch/sh/include/asm/hd64461.h
Extension
.h
Size
12075 bytes
Lines
253
Domain
Architecture Layer
Bucket
arch/sh
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __ASM_SH_HD64461
#define __ASM_SH_HD64461
/*
 *	Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
 *	Copyright (C) 2004 Paul Mundt
 *	Copyright (C) 2000 YAEGASHI Takeshi
 *
 *		Hitachi HD64461 companion chip support
 *	(please note manual reference 0x10000000 = 0xb0000000)
 */

/* Constants for PCMCIA mappings */
#define	HD64461_PCC_WINDOW	0x01000000

/* Area 6 - Slot 0 - memory and/or IO card */
#define HD64461_IOBASE		0xb0000000
#define HD64461_IO_OFFSET(x)	(HD64461_IOBASE + (x))
#define	HD64461_PCC0_BASE	HD64461_IO_OFFSET(0x8000000)
#define	HD64461_PCC0_ATTR	(HD64461_PCC0_BASE)				/* 0xb80000000 */
#define	HD64461_PCC0_COMM	(HD64461_PCC0_BASE+HD64461_PCC_WINDOW)		/* 0xb90000000 */
#define	HD64461_PCC0_IO		(HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW)	/* 0xba0000000 */

/* Area 5 - Slot 1 - memory card only */
#define	HD64461_PCC1_BASE	HD64461_IO_OFFSET(0x4000000)
#define	HD64461_PCC1_ATTR	(HD64461_PCC1_BASE)				/* 0xb4000000 */
#define	HD64461_PCC1_COMM	(HD64461_PCC1_BASE+HD64461_PCC_WINDOW)		/* 0xb5000000 */

/* Standby Control Register for HD64461 */
#define	HD64461_STBCR			HD64461_IO_OFFSET(0x00000000)
#define	HD64461_STBCR_CKIO_STBY		0x2000
#define	HD64461_STBCR_SAFECKE_IST	0x1000
#define	HD64461_STBCR_SLCKE_IST		0x0800
#define	HD64461_STBCR_SAFECKE_OST	0x0400
#define	HD64461_STBCR_SLCKE_OST		0x0200
#define	HD64461_STBCR_SMIAST		0x0100
#define	HD64461_STBCR_SLCDST		0x0080
#define	HD64461_STBCR_SPC0ST		0x0040
#define	HD64461_STBCR_SPC1ST		0x0020
#define	HD64461_STBCR_SAFEST		0x0010
#define	HD64461_STBCR_STM0ST		0x0008
#define	HD64461_STBCR_STM1ST		0x0004
#define	HD64461_STBCR_SIRST		0x0002
#define	HD64461_STBCR_SURTST		0x0001

/* System Configuration Register */
#define	HD64461_SYSCR		HD64461_IO_OFFSET(0x02)

/* CPU Data Bus Control Register */
#define	HD64461_SCPUCR		HD64461_IO_OFFSET(0x04)

/* Base Address Register */
#define	HD64461_LCDCBAR		HD64461_IO_OFFSET(0x1000)

/* Line increment address */
#define	HD64461_LCDCLOR		HD64461_IO_OFFSET(0x1002)

/* Controls LCD controller */
#define	HD64461_LCDCCR		HD64461_IO_OFFSET(0x1004)

/* LCCDR control bits */
#define	HD64461_LCDCCR_STBACK	0x0400	/* Standby Back */
#define	HD64461_LCDCCR_STREQ	0x0100	/* Standby Request */
#define	HD64461_LCDCCR_MOFF	0x0080	/* Memory Off */
#define	HD64461_LCDCCR_REFSEL	0x0040	/* Refresh Select */
#define	HD64461_LCDCCR_EPON	0x0020	/* End Power On */
#define	HD64461_LCDCCR_SPON	0x0010	/* Start Power On */

/* Controls LCD (1) */
#define	HD64461_LDR1		HD64461_IO_OFFSET(0x1010)
#define	HD64461_LDR1_DON	0x01	/* Display On */
#define	HD64461_LDR1_DINV	0x80	/* Display Invert */

/* Controls LCD (2) */
#define	HD64461_LDR2		HD64461_IO_OFFSET(0x1012)
#define	HD64461_LDHNCR		HD64461_IO_OFFSET(0x1014)	/* Number of horizontal characters */
#define	HD64461_LDHNSR		HD64461_IO_OFFSET(0x1016)	/* Specify output start position + width of CL1 */
#define	HD64461_LDVNTR		HD64461_IO_OFFSET(0x1018)	/* Specify total vertical lines */
#define	HD64461_LDVNDR		HD64461_IO_OFFSET(0x101a)	/* specify number of display vertical lines */
#define	HD64461_LDVSPR		HD64461_IO_OFFSET(0x101c)	/* specify vertical synchronization pos and AC nr */

/* Controls LCD (3) */
#define	HD64461_LDR3		HD64461_IO_OFFSET(0x101e)

/* Palette Registers */
#define	HD64461_CPTWAR		HD64461_IO_OFFSET(0x1030)	/* Color Palette Write Address Register */
#define	HD64461_CPTWDR		HD64461_IO_OFFSET(0x1032)	/* Color Palette Write Data Register */
#define	HD64461_CPTRAR		HD64461_IO_OFFSET(0x1034)	/* Color Palette Read Address Register */
#define	HD64461_CPTRDR		HD64461_IO_OFFSET(0x1036)	/* Color Palette Read Data Register */

#define	HD64461_GRDOR		HD64461_IO_OFFSET(0x1040)	/* Display Resolution Offset Register */

Annotation

Implementation Notes