arch/sh/include/cpu-sh2a/cpu/sh7264.h
Source file repositories/reference/linux-study-clean/arch/sh/include/cpu-sh2a/cpu/sh7264.h
File Facts
- System
- Linux kernel
- Corpus path
arch/sh/include/cpu-sh2a/cpu/sh7264.h- Extension
.h- Size
- 5259 bytes
- Lines
- 170
- Domain
- Architecture Layer
- Bucket
- arch/sh
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef __ASM_SH7264_H__
#define __ASM_SH7264_H__
enum {
/* Port A */
GPIO_PA3, GPIO_PA2, GPIO_PA1, GPIO_PA0,
/* Port B */
GPIO_PB22, GPIO_PB21, GPIO_PB20,
GPIO_PB19, GPIO_PB18, GPIO_PB17, GPIO_PB16,
GPIO_PB15, GPIO_PB14, GPIO_PB13, GPIO_PB12,
GPIO_PB11, GPIO_PB10, GPIO_PB9, GPIO_PB8,
GPIO_PB7, GPIO_PB6, GPIO_PB5, GPIO_PB4,
GPIO_PB3, GPIO_PB2, GPIO_PB1,
/* Port C */
GPIO_PC10, GPIO_PC9, GPIO_PC8,
GPIO_PC7, GPIO_PC6, GPIO_PC5, GPIO_PC4,
GPIO_PC3, GPIO_PC2, GPIO_PC1, GPIO_PC0,
/* Port D */
GPIO_PD15, GPIO_PD14, GPIO_PD13, GPIO_PD12,
GPIO_PD11, GPIO_PD10, GPIO_PD9, GPIO_PD8,
GPIO_PD7, GPIO_PD6, GPIO_PD5, GPIO_PD4,
GPIO_PD3, GPIO_PD2, GPIO_PD1, GPIO_PD0,
/* Port E */
GPIO_PE5, GPIO_PE4,
GPIO_PE3, GPIO_PE2, GPIO_PE1, GPIO_PE0,
/* Port F */
GPIO_PF12,
GPIO_PF11, GPIO_PF10, GPIO_PF9, GPIO_PF8,
GPIO_PF7, GPIO_PF6, GPIO_PF5, GPIO_PF4,
GPIO_PF3, GPIO_PF2, GPIO_PF1, GPIO_PF0,
/* Port G */
GPIO_PG24,
GPIO_PG23, GPIO_PG22, GPIO_PG21, GPIO_PG20,
GPIO_PG19, GPIO_PG18, GPIO_PG17, GPIO_PG16,
GPIO_PG15, GPIO_PG14, GPIO_PG13, GPIO_PG12,
GPIO_PG11, GPIO_PG10, GPIO_PG9, GPIO_PG8,
GPIO_PG7, GPIO_PG6, GPIO_PG5, GPIO_PG4,
GPIO_PG3, GPIO_PG2, GPIO_PG1, GPIO_PG0,
/* Port H - Port H does not have a Data Register */
/* Port I - not on device */
/* Port J */
GPIO_PJ11, GPIO_PJ10, GPIO_PJ9, GPIO_PJ8,
GPIO_PJ7, GPIO_PJ6, GPIO_PJ5, GPIO_PJ4,
GPIO_PJ3, GPIO_PJ2, GPIO_PJ1, GPIO_PJ0,
/* Port K */
GPIO_PK11, GPIO_PK10, GPIO_PK9, GPIO_PK8,
GPIO_PK7, GPIO_PK6, GPIO_PK5, GPIO_PK4,
GPIO_PK3, GPIO_PK2, GPIO_PK1, GPIO_PK0,
/* INTC: IRQ and PINT on PB/PD/PE */
GPIO_FN_PINT7_PG, GPIO_FN_PINT6_PG, GPIO_FN_PINT5_PG, GPIO_FN_PINT4_PG,
GPIO_FN_PINT3_PG, GPIO_FN_PINT2_PG, GPIO_FN_PINT1_PG,
GPIO_FN_IRQ7_PC, GPIO_FN_IRQ6_PC, GPIO_FN_IRQ5_PC, GPIO_FN_IRQ4_PC,
GPIO_FN_IRQ3_PG, GPIO_FN_IRQ2_PG, GPIO_FN_IRQ1_PJ, GPIO_FN_IRQ0_PJ,
GPIO_FN_IRQ3_PE, GPIO_FN_IRQ2_PE, GPIO_FN_IRQ1_PE, GPIO_FN_IRQ0_PE,
/* WDT */
GPIO_FN_WDTOVF,
/* CAN */
GPIO_FN_CTX1, GPIO_FN_CRX1, GPIO_FN_CTX0, GPIO_FN_CTX0_CTX1,
GPIO_FN_CRX0, GPIO_FN_CRX0_CRX1,
/* DMAC */
GPIO_FN_TEND0, GPIO_FN_DACK0, GPIO_FN_DREQ0,
GPIO_FN_TEND1, GPIO_FN_DACK1, GPIO_FN_DREQ1,
/* ADC */
GPIO_FN_ADTRG,
/* BSC */
GPIO_FN_A25, GPIO_FN_A24,
GPIO_FN_A23, GPIO_FN_A22, GPIO_FN_A21, GPIO_FN_A20,
GPIO_FN_A19, GPIO_FN_A18, GPIO_FN_A17, GPIO_FN_A16,
GPIO_FN_A15, GPIO_FN_A14, GPIO_FN_A13, GPIO_FN_A12,
GPIO_FN_A11, GPIO_FN_A10, GPIO_FN_A9, GPIO_FN_A8,
GPIO_FN_A7, GPIO_FN_A6, GPIO_FN_A5, GPIO_FN_A4,
GPIO_FN_A3, GPIO_FN_A2, GPIO_FN_A1, GPIO_FN_A0,
Annotation
- Atlas domain: Architecture Layer / arch/sh.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.