arch/sh/include/cpu-sh4/cpu/sh7785.h

Source file repositories/reference/linux-study-clean/arch/sh/include/cpu-sh4/cpu/sh7785.h

File Facts

System
Linux kernel
Corpus path
arch/sh/include/cpu-sh4/cpu/sh7785.h
Extension
.h
Size
5473 bytes
Lines
261
Domain
Architecture Layer
Bucket
arch/sh
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __ASM_SH7785_H__
#define __ASM_SH7785_H__

/* Boot Mode Pins:
 *
 * MODE0: CPG - Initial Pck/Bck Frequency [FRQMR1]
 * MODE1: CPG - Initial Uck/SHck/DDRck Frequency [FRQMR1]
 * MODE2: CPG - Reserved (L: Normal operation)
 * MODE3: CPG - Reserved (L: Normal operation)
 * MODE4: CPG - Initial PLL setting (72x/36x)
 * MODE5: LBSC - Area0 Memory Type / Bus Width [CS0BCR.8]
 * MODE6: LBSC - Area0 Memory Type / Bus Width [CS0BCR.9]
 * MODE7: LBSC - Area0 Memory Type / Bus Width [CS0BCR.3]
 * MODE8: LBSC - Endian Mode (L: Big, H: Little) [BCR.31]
 * MODE9: LBSC - Master/Slave Mode (L: Slave) [BCR.30]
 * MODE10: CPG - Clock Input (L: Ext Clk, H: Crystal)
 * MODE11: PCI - Pin Mode (LL: PCI host, LH: PCI slave)
 * MODE12: PCI - Pin Mode (HL: Local bus, HH: DU)
 * MODE13: Boot Address Mode (L: 29-bit, H: 32-bit)
 * MODE14: Reserved (H: Normal operation)
 *
 * More information in sh7785 manual Rev.1.00, page 1628.
 */

/* Pin Function Controller:
 * GPIO_FN_xx - GPIO used to select pin function
 * GPIO_Pxx - GPIO mapped to real I/O pin on CPU
 */
enum {
	/* PA */
	GPIO_PA7, GPIO_PA6, GPIO_PA5, GPIO_PA4,
	GPIO_PA3, GPIO_PA2, GPIO_PA1, GPIO_PA0,

	/* PB */
	GPIO_PB7, GPIO_PB6, GPIO_PB5, GPIO_PB4,
	GPIO_PB3, GPIO_PB2, GPIO_PB1, GPIO_PB0,

	/* PC */
	GPIO_PC7, GPIO_PC6, GPIO_PC5, GPIO_PC4,
	GPIO_PC3, GPIO_PC2, GPIO_PC1, GPIO_PC0,

	/* PD */
	GPIO_PD7, GPIO_PD6, GPIO_PD5, GPIO_PD4,
	GPIO_PD3, GPIO_PD2, GPIO_PD1, GPIO_PD0,

	/* PE */
	GPIO_PE5, GPIO_PE4, GPIO_PE3, GPIO_PE2,
	GPIO_PE1, GPIO_PE0,

	/* PF */
	GPIO_PF7, GPIO_PF6, GPIO_PF5, GPIO_PF4,
	GPIO_PF3, GPIO_PF2, GPIO_PF1, GPIO_PF0,

	/* PG */
	GPIO_PG7, GPIO_PG6, GPIO_PG5, GPIO_PG4,
	GPIO_PG3, GPIO_PG2, GPIO_PG1, GPIO_PG0,

	/* PH */
	GPIO_PH7, GPIO_PH6, GPIO_PH5, GPIO_PH4,
	GPIO_PH3, GPIO_PH2, GPIO_PH1, GPIO_PH0,

	/* PJ */
	GPIO_PJ7, GPIO_PJ6, GPIO_PJ5, GPIO_PJ4,
	GPIO_PJ3, GPIO_PJ2, GPIO_PJ1, GPIO_PJ0,

	/* PK */
	GPIO_PK7, GPIO_PK6, GPIO_PK5, GPIO_PK4,
	GPIO_PK3, GPIO_PK2, GPIO_PK1, GPIO_PK0,

	/* PL */
	GPIO_PL7, GPIO_PL6, GPIO_PL5, GPIO_PL4,
	GPIO_PL3, GPIO_PL2, GPIO_PL1, GPIO_PL0,

	/* PM */
	GPIO_PM1, GPIO_PM0,

	/* PN */
	GPIO_PN7, GPIO_PN6, GPIO_PN5, GPIO_PN4,
	GPIO_PN3, GPIO_PN2, GPIO_PN1, GPIO_PN0,

	/* PP */
	GPIO_PP5, GPIO_PP4,
	GPIO_PP3, GPIO_PP2, GPIO_PP1, GPIO_PP0,

	/* PQ */
	GPIO_PQ4,
	GPIO_PQ3, GPIO_PQ2, GPIO_PQ1, GPIO_PQ0,

	/* PR */
	GPIO_PR3, GPIO_PR2, GPIO_PR1, GPIO_PR0,

Annotation

Implementation Notes