arch/sh/include/mach-dreamcast/mach/dma.h
Source file repositories/reference/linux-study-clean/arch/sh/include/mach-dreamcast/mach/dma.h
File Facts
- System
- Linux kernel
- Corpus path
arch/sh/include/mach-dreamcast/mach/dma.h- Extension
.h- Size
- 702 bytes
- Lines
- 30
- Domain
- Architecture Layer
- Bucket
- arch/sh
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef __ASM_SH_DREAMCAST_DMA_H
#define __ASM_SH_DREAMCAST_DMA_H
/* Number of DMA channels */
#define G2_NR_DMA_CHANNELS 4
/* Channels for cascading */
#define PVR2_CASCADE_CHAN 2
#define G2_CASCADE_CHAN 3
/* PVR2 DMA Registers */
#define PVR2_DMA_BASE 0xa05f6800
#define PVR2_DMA_ADDR (PVR2_DMA_BASE + 0)
#define PVR2_DMA_COUNT (PVR2_DMA_BASE + 4)
#define PVR2_DMA_MODE (PVR2_DMA_BASE + 8)
#define PVR2_DMA_LMMODE0 (PVR2_DMA_BASE + 132)
#define PVR2_DMA_LMMODE1 (PVR2_DMA_BASE + 136)
/* G2 DMA Register */
#define G2_DMA_BASE 0xa05f7800
#endif /* __ASM_SH_DREAMCAST_DMA_H */
Annotation
- Atlas domain: Architecture Layer / arch/sh.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.