arch/sh/kernel/cpu/sh4a/clock-sh7734.c

Source file repositories/reference/linux-study-clean/arch/sh/kernel/cpu/sh4a/clock-sh7734.c

File Facts

System
Linux kernel
Corpus path
arch/sh/kernel/cpu/sh4a/clock-sh7734.c
Extension
.c
Size
8931 bytes
Lines
257
Domain
Architecture Layer
Bucket
arch/sh
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * arch/sh/kernel/cpu/sh4a/clock-sh7734.c
 *
 * Clock framework for SH7734
 *
 * Copyright (C) 2011, 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
 * Copyright (C) 2011, 2012 Renesas Solutions Corp.
 */

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/clkdev.h>
#include <linux/delay.h>
#include <asm/clock.h>
#include <asm/freq.h>

static struct clk extal_clk = {
	.rate       = 33333333,
};

#define MODEMR          (0xFFCC0020)
#define MODEMR_MASK     (0x6)
#define MODEMR_533MHZ   (0x2)

static unsigned long pll_recalc(struct clk *clk)
{
	int mode = 12;
	u32 r = __raw_readl(MODEMR);

	if ((r & MODEMR_MASK) & MODEMR_533MHZ)
		mode = 16;

	return clk->parent->rate * mode;
}

static struct sh_clk_ops pll_clk_ops = {
	.recalc		= pll_recalc,
};

static struct clk pll_clk = {
	.ops        = &pll_clk_ops,
	.parent     = &extal_clk,
	.flags      = CLK_ENABLE_ON_INIT,
};

static struct clk *main_clks[] = {
	&extal_clk,
	&pll_clk,
};

static int multipliers[] = { 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
static int divisors[] = { 1, 3, 2, 3, 4, 6, 8, 9, 12, 16, 18, 24 };

static struct clk_div_mult_table div4_div_mult_table = {
	.divisors = divisors,
	.nr_divisors = ARRAY_SIZE(divisors),
	.multipliers = multipliers,
	.nr_multipliers = ARRAY_SIZE(multipliers),
};

static struct clk_div4_table div4_table = {
	.div_mult_table = &div4_div_mult_table,
};

enum { DIV4_I, DIV4_S, DIV4_B, DIV4_M, DIV4_S1, DIV4_P, DIV4_NR };

#define DIV4(_reg, _bit, _mask, _flags) \
	SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)

struct clk div4_clks[DIV4_NR] = {
	[DIV4_I] = DIV4(FRQMR1, 28, 0x0003, CLK_ENABLE_ON_INIT),
	[DIV4_S] = DIV4(FRQMR1, 20, 0x000C, CLK_ENABLE_ON_INIT),
	[DIV4_B] = DIV4(FRQMR1, 16, 0x0140, CLK_ENABLE_ON_INIT),
	[DIV4_M] = DIV4(FRQMR1, 12, 0x0004, CLK_ENABLE_ON_INIT),
	[DIV4_S1] = DIV4(FRQMR1, 4, 0x0030, CLK_ENABLE_ON_INIT),
	[DIV4_P] = DIV4(FRQMR1, 0, 0x0140, CLK_ENABLE_ON_INIT),
};

#define MSTPCR0	0xFFC80030
#define MSTPCR1	0xFFC80034
#define MSTPCR3	0xFFC8003C

enum {
	MSTP030, MSTP029, /* IIC */
	MSTP026, MSTP025, MSTP024, /* SCIF */
	MSTP023,
	MSTP022, MSTP021,
	MSTP019, /* HSCIF */

Annotation

Implementation Notes